TLK2208B Datasheet, PDF (21/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
transmit logic (continued)
8b/10b encoder
All true serial interfaces require a method of encoding to ensure sufficient transition density for the receiving
PLL to acquire and maintain lock. The encoding scheme also maintains the signal dc balance by keeping the
number of 1s and 0s the same, which allows for ac-coupled data transmission. The TLK2208B uses the 8b/10b
encoding algorithm that is used by the Fibre Channel and Gigabit Ethernet specifications. This provides good
transition density for clock recovery and improves error checking. The 8b/10b encoder/decoder function is
enabled for all channels by the assertion of the CODE terminal. When enabled, the TLK2208B internally
encodes and decodes the data such that the user actually reads and writes 8-bit data on each channel.
When enabled (CODE = high), the 8b/10b encoder converts 8-bit-wide data to a 10-bit-wide encoded data
character to improve its transition density. This transmission code includes D-characters, used for transmitting
data, and K-characters, used for transmitting protocol information. Each K- or D-character code word can also
have either a positive or a negative disparity version. The disparity of a code word is selected by the encoder
to balance the running disparity of the serialized data stream.
The generation of K-characters to be transmitted on each channel is controlled by TDxx8 when in the
multiplexed channel mode. When these terminals are asserted along with the 8 bits of data, an 8b/10b
K-character is transmitted. Similarly, reception of K-characters is reported by RDxx8. When RDxx8 is asserted,
the 8 bits of data on RDxx should be interpreted as a K-character. The TLK2208B transmits and receives all
12 of the valid K-characters defined in the Fibre Channel and Gigabit Ethernet specifications. Invalid data
patterns input when TDxx8 is asserted result in an invalid K-character being transmitted, which results in an
code error at the receiver.
serializer
The parallel-to-serial shift register on each channel takes in 10-bit-wide data from either the 8b/10b encoders,
if enabled, or directly from the transmit data bus, and converts it to a serial stream. The shift register is clocked
by the internally generated bit clock, which is 10 times the reference-clock (REFCLK) frequency. The
least-significant bit (LSB) for each channel is transmitted first.
receive logic
The receiver input data must be ac-coupled and have a rate of 1.0–1.3 Gbps. Resistive termination to match
50-Ω traces is on-chip. The clock recovery circuitry retimes the input data by extracting a clock from the input
data, and passes on the serial data and this recovered clock to the deserializer. Byte alignment is performed
on K-characters per IEEE 802.3z (see the byte alignment logic section for details).
receive parallel interface
The receive data bus for all channels is output source centered with the bus clock in the center of the data eye,
allowing direct connection to the protocol device.
In multiplexed channel and nibble interface synchronized channel modes, parallel data to be transferred to the
protocol device is output referenced to both the rising and falling edges of RCLK. RCLK is frequency
synchronous with REFCLK, but has no set phase relationship with respect to REFCLK.
In multiplexed channel mode, channels A and B, C and D, E and F, and G and H are each paired and interleaved
on the same 10-bit bus. Channels B, D, F, H are output referenced to the rising edge of RCLK/RBCH and falling
edge of RBCG (see Figure 6). Channels A, C, E, and G are output referenced to the falling edge of RCLK/RBCH
and rising edge of RBCG. Remaining clocks RBCE−RBCF, RBCC−RBCD, and RBCA−RBCB are identical
copies of RCLK/RBCH–RBCG and could be used as complementary clock pairs.
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