TLK2208B Datasheet, PDF (31/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
Table 24. Status Register 3 (0x1D) Bit Definitions
BIT(S)
DEFAULT
VALUE = 0x0000
NAME
DESCRIPTION
READ/WRITE
29.15:8 00h
RX_SwRst[7:0]
Individual receive channel reset
Resets channel when set to logic high
Read/write,
self-clearing,
See Note 5
29.7:0 00h
TX_SwRst[7:0]
Individual transmit channel reset
Resets channel when set to logic high
Read/write,
self-clearing,
See Note 5
NOTE 5: After these bits are set to 1, they automatically set themselves back to 0 on the next MDC clock cycle. Note: In the transmit direction,
channel pairs (A/B, C/D, E/F, G/H) have a common transmit clock and DDR input register bank. As a result, software assertion of the
Channel A TX_SwRST MDIO register will temporarily corrupt Channel B data (until the software reset ends). Channel C TX_SwRST
causes the same data corruption on Channel D. Channel E TX_SwRST causes the same data corruption on Channel F. Channel G
TX_SwRST causes the same data corruption on Channel H.
Table 25. Test Register 1 (0x1E) Bit Definitions
BIT(S)
30.15:8
30.7
30.6
30.5
30.4
30.3
30.2
30.1:0
DEFAULT
VALUE = 0x000B
00h
0b
0b
0b
0b
1b
0b
11b
NAME
TI_TST[7:0]
Reserved
ASYPHRCTL
BCLK_RST
TCLK_EN
LOCK2RX
PHRPOL
PHRMAG[1:0]
Reserved for TI testing
Reserved for TI testing
Reserved for TI testing
Reserved for TI testing
Reserved for TI testing
Reserved for TI testing
Reserved for TI testing
Reserved for TI testing
DESCRIPTION
READ/WRITE
Read/write
Read-only
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Table 26. Test Register 1 (0x1F) Bit Definitions
BIT(S)
31.15:8
31.7:0
DEFAULT
VALUE = 0x0000
00h
00h
NAME
DESCRIPTION
READ/WRITE
RX PRBS_Pass[H:A] PRBS pass information for all RX channels H through A
Read-only
TX PRBS_Pass[H:A] PRBS pass information for all TX channels H through A (reserved Read-only
for TI testing)
JTAG interface
The TLK2208B provides the full five-terminal JTAG interface as defined in IEEE 1149.1 to support
manufacturing test.
serial loopback
The TLK2208B can provide a self-test function by enabling the internal serial loopback path for all channels with
the assertion of LPBK. The loopback for individual channels can be enabled via the MDIO registers (22.15:8).
The parallel data output can be compared to the parallel input data for that channel to perform functional
verification. The external differential output is held in a high-impedance state during the serial loopback testing.
Incoming data on the serial interface is disregarded.
far-end loopback
The TLK2208B can provide a self-test function by enabling the internal far-end loopback path for all or pairs of
channels with the assertion of MDIO register bits 22.7:0. The serial data output can be compared to the serial
input data for selected channels to perform functional verification of high-speed RX and TX. The parallel input
data during the far-end loopback test is disregarded. The external parallel outputs are held in a high-impedance
state during the far-end loopback testing.
WWW.TI.COM
31