GC4114 Datasheet, PDF (9/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
Very Important Note: The chip assumes that the serial clock is continuous, and does not stop between
transfers. The SCK clock may stop, but must be active when frame sync occurs, and be active for one cycle after
the last bit is sent. Serial data can be sent using only 32 bit clocks per REQ period if the frame sync for the 16 bit I
word (or the 32 bit I/Q word in the PACKED mode) is synchronized to occur between 7 and 2 bit periods before REQ.
The user can choose to operate the serial lines as either 3.3 or 5 volt logic levels to facilitate the interface
of the GC4114 chip with external circuitry.
3.2.2 Memory Mapped Interfaced
Input samples can be entered into the chip using the control interface. Addresses 16 through 31 are the
input data registers. Note that these registers can be written to in a DMA burst, 8 bits at a time. Note that some DMA
formats write samples most significant byte first. If this is the case then the DMA should write from address 31 down
to address 16. The REQ strobe from the GC4114 chip defines when the DMA transfer can start. The transfer must
be done before the next REQ strobe is received.
3.3 GAIN
Each input sample is multiplied by an 8 bit 2’s complement gain word. If the gain word is ‘G’, which ranges
from -128 to +127, then the gain adjustment will be G/128. This gives a 42 dB gain adjustment range. Setting G to
zero clears the channel. A different gain can be specified for each channel. Gain is described in more detail in
Section 3.7.
3.4 THE UP-CONVERTERS
Each up-converter channel uses a two stage interpolate by four filter and a 4 stage cascaded
integrate-comb (CIC) filter to increase the sample rate of the input data up to a sample rate equal to the chip’s clock
rate. An NCO and mixer circuit to modulate the signal up to the desired center frequency. A block diagram of each
up-convert channel is shown below:
I
FROM
INPUT
FORMATTER
Q
TUNING
FREQUENCY
PHASE
OFFSET
cosine
sine
NCO
OUT
Figure 4. The Up-converter Channel
After the gain has been applied, as described in the previous section, the input data is interpolated by a
factor of 2 in a 63 tap filter with programmable coefficients (PFIR). The user can choose between an internal default
filter shape for the PFIR, or can download a custom set of taps. A typical use of the user down loaded coefficients
is to implement matched (root-raised-cosine) transmit filters.
Texas Instruments Inc.
-5-
MAY 22, 2000
This document contains information which may be changed at any time without notice