GC4114 Datasheet, PDF (12/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
The output of the CIC interpolation filter is equal to the clock rate. The CIC filter has a gain equal to N³ which
must be removed by the “SCALE AND ROUND” circuit shown in Figure 6. This circuit has a gain equal to
2^{-(3+SCALE+12*BIG_SHIFT)}, where SCALE ranges from 0 to 15 and BIG_SHIFT ranges from 0 to 2. The value chosen
for BIG_SHIFT must also satisfy: 2^{(12*BIG_SHIFT+18)} ≥ N³. Overflows due to improper gain settings will go undetected
if this relationship is violated. This restriction means that BIG_SHIFT = 0 for N between 8 and 64, BIG_SHIFT = 1
for N between 65 and 1024, and BIG_SHIFT = 2 for N between 1025 and 16384.
The CIC filter must be initialized when the chip is first configured or whenever the interpolation value N or
the shift value BIG_SHIFT are changed. The CIC filter is initialized using the flush controls described in Section 5.8.
If the CIC is disturbed during processing due to noise, radiation particles, or due to changing N or BIG_SHIFT, then
it will become unstable and generate wideband white noise in the output. This instability can be prevented by using
the “auto flush” capability of the chip¹ (See control register 2, bit 6 in Section 5.3). The auto flush mode detects the
CIC instability and automatically re-initializes the CIC. The auto flush mode requires that the gain up to the output
of the CIC filter is less than or equal to unity.
3.4.4 The Sine/Cosine Generator
The tuning frequency of each up-converter is specified as a 32 bit word and the phase offset is specified
as a 16 bit word. The tuners can be synchronized with tuners on other chips. This allows multiple up-converter
outputs to be coherently combined, each with a unique phase and amplitude. A block diagram of the NCO
(Numerically Controlled Oscillator) circuit is shown in Figure 7.
FREQUENCY ^{32 BITS}
WORD
PHASE
DITHER
OFFSET ^GENERATOR
32 BITS
16 BITS
5 BITS
18 MSBs
14 MSBs
SINE/COSINE
LOOKUP
TABLE
13 BITS _SINE/COSINE
OUT
Figure 7. NCO Circuit
The NCO’s spur level is reduced to below 90 dB through the use of phase dithering. Figure 8 shows an
example NCO output with and without dithering. Notice that the spur level without dithering is about -82 dB, and the
spur level with dithering is well below -90 dB.
The tuning frequency is set according to the formula FREQ = 2³²F/F_CK, where F is the desired tuning
frequency and F_CK is the chip’s clock rate. The 16 bit phase offset setting is PHASE = 2¹⁶P/2π, where P is the
desired phase in radians ranging between 0 and 2π
1. The auto flush mode is a patent pending feature of the chip.
Texas Instruments Inc.
-8-
MAY 22, 2000
This document contains information which may be changed at any time without notice