GC4114 Datasheet, PDF (34/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
Table 10: 1X QPSK Configuration
Control Registers
Channel, Status and Coefficient Pages
Address
Data
Address
Page 0
Page 1
Page 2
Page 3
00 (HEX)
65 (HEX)¹
20 (HEX)
A FREQ[0:7]
00
1B
8B
01
00->02²
21
A FREQ[8:15]
read only
00
FF
02
5D
22
A FREQ[16:23]
EC
08
03
57
23
A FREQ[24:31]
FF
00
04
02
24
00
05
01⁵
25
00
FA
70
FF
00
06
57
26
31
22
51
07
02
27
00
FF
08
5F
28
B FREQ[0:7]
E2
52
09
5F
29
B FREQ[8:15]
FF
00
0A
5F
2A
B FREQ[16:23]
F7
E0
0B
5F
1B
B FREQ[24:31]
FF
00
0C
55
2C
00
0D
0A, 02, 82³
2D
00
0E
P8⁴
2E
31
27
A4
00
FE
DB
3D
0F
read only
2F
FF
00
10
00
30
C FREQ[0:7]
FF
1E
11
00
31
C FREQ[8:15]
FF
01
12
00
32
C FREQ[16:23]
34
07
13
00
33
C FREQ[24:31]
00
FD
14
00
34
00
C9
FE
15
00
35
00
FF
02
16
00
36
31
FB
AC
17
00
37
FF
06
18
00
38
D FREQ[0:7]
3E
36
19
00
39
D FREQ[8:15]
00
F0
1A
00
3A
D FREQ[16:23]
B8
1B
1B
00
3B
D FREQ[24:31]
FF
F6
1C
00
3C
00
0F
01
1D
00
3D
00
00
47
1E
00
3E
31
5C
FF
1F
00
3F
00
7F
1. Initialize to 65 in chip U0 (Master) while configuring the chips, then set to E5 to fire off the one shot pulse, then
back to 65.This assumes that SO is tied to SI of all four chips
2. Initialize to 00, then set to 02 after generating the one shot pulse.
3 Chip U0 uses 0A for SUM_CLR, U1 and U2 use 02 for sum I/O mode, and U3 uses 82 for round to 14 bits.
4. “P” is the page number. The lower nibble should stay at “8¨.
5. Serial interface dependent.
The initialization procedure is to load all control and coefficient registers in all four chips as shown in Table
10, and then to synchronize all of the chips using the one shot pulse from chip U0, and then to go back and write
02_HEX into address 1 of each chip to select the downloaded coefficients. The one shot pulse is generated by setting
address 0 in chip U0 to E5_HEX and then back to 65_HEX.
7.5.2 Modulating a 25K-Baud QPSK signal in the 2X Mode
This section illustrates how to modulate signals in the 2X mode. The signal parameters are the same as
shown in Tables 8 and 9 except that the data is entered into the chip at twice the baud rate (50 KHz) by alternating
Texas Instruments Inc.
- 30 -
MAY 22, 2000
This document contains information which may be changed at any time without notice