GC4114 Datasheet, PDF (7/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
Figure 2 shows timing diagrams illustrating both I/O modes.
CE
WR
RD
A[0-5]
C[0-7]
t_CSU
t_CSU
t_CDLY
READ CYCLE- NORMAL MODE
t_CHD
t_CZ
CE
WR
RD
A[0-5]
C[0-7]
t_CSU
t_CSU
t_CSPW
WRITE CYCLE- NORMAL MODE
t_CHD
CE
WR
A[0-5]
C[0-7]
t_CSU
t_CDLY
READ CYCLE- RD HELD LOW
t_CHD
t_CZ
CE
WR
A[0-5]
C[0-7]
t_CSU
t_CSPW
WRITE CYCLE- RD HELD LOW
t_CHD
Figure 2. Control I/O Timing
The setup, hold and pulse width requirements for control read or write operations are given in
Section 6.0.
The C, A, WR, RD and CE pins will accept either 5 volt or 3.3 volt input levels. Separate power supply pins
(V_UP) are provided on the chip to enable this feature.
3.2 INPUT FORMAT
The input samples are 16 bits, either real or complex, in 2’s complement format. The samples are input to
the chip either through the bit-serial input ports, or through memory mapped control registers.
3.2.1 Bit Serial Interface
The bit serial format consists of a data input pin, a bit clock pin, and a frame strobe pin for each of the four
channels, and a data request pin which is common to all channels. The input accepts either individual 16 bit words
in a format compatible with almost all DSP chips, or as the upper 16 bits of 32 bit words, or as two 16 bit words
packed into a 32 bit word. The bit serial data is always entered MSB first. Complex values are entered I-half first
followed by the Q-half, either as two separate transfers, or as a single 32 bit word with the I-half in the MSBs and
the Q-half in the LSBs. Real values can be entered as 16 bit words or 32 bit words. In the 32 bit mode each 16 bit
Texas Instruments Inc.
-3-
MAY 22, 2000
This document contains information which may be changed at any time without notice