GC4114 Datasheet, PDF (18/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
5.0 CONTROL REGISTERS
The chip is configured and controlled through the use of eight bit control registers. These registers are
accessed for reading or writing using the control bus pins (CE, RD, WR, A[0:5], and C[0:7]) described in the
previous section. The register names and their addresses are:
The Mode and Control Registers are addresses 0 to 15
ADDRESS NAME
ADDRESS
NAME
0
Sync Mode
1
Interpolation Mode
2
Interpolation Gain
3
Interpolation Byte 0
4
Interpolation Byte 1
5
Input Mode
6
Counter Byte 0
7
Counter Byte 1
8
Channel A Sync
9
Channel B Sync
10
Channel C Sync
11
Channel D Sync
12
Channel Flush Mode
13
Summer Mode
14
Status
15
Checksum
The Input registers are addresses 16 to 31. The 16 bit inputs are stored least significant byte in the first
address, the most significant in the second.
ADDRESSES NAME
ADDRESSES NAME
16,17
18,19
20,21
22,23
Channel A, I-input
Channel A, Q-input
Channel B, I-input
Channel B, Q-input
24,25
26,27
28,29
30,31
Channel C, I-input
Channel C, Q-input
Channel D, I-input
Channel D, Q-input
Addresses 32 to 63 are used in four modes as determined by the page select control bits in the status
register. Page zero is the frequency, phase and gain settings for the four channels. Page one is for monitoring status
and test points. Pages two and three are used to store the coefficients for the programmable interpolate by two filter.
The Page zero register assignments are:
ADDRESSES NAME
ADDRESSES NAME
32,33,34,35
36,37
38
39
40,41,42,43
44,45
46
47
Channel A Frequency
Channel A Phase
Channel A Gain
unused
Channel B Frequency
Channel B Phase
Channel B Gain
unused
48,49,50,51
52,53
54
55
56,57,58,59
60,61
62
63
Channel C Frequency
Channel C Phase
Channel C Gain
unused
Channel D Frequency
Channel D Phase
Channel D Gain
unused
The 32 fir filter coefficients are stored as two bytes per 16 bit word in 2’s complement format. The least
significant 8 bits in the lower byte and the most significant 8 bits in the upper byte. Page two stores coefficients 0
through 15 in addresses 32 to 63. Page three stores coefficients 16 to 31. Coefficient 31 is the center tap. The lower
byte of the coefficient must be loaded and then the upper byte.
The following sections describe each of these registers. The type of each register bit is either R, W, or R/W
indicating whether the bit is read only, write only, or read/write. All bits are active high.
Texas Instruments Inc.
- 14 -
MAY 22, 2000
This document contains information which may be changed at any time without notice