GC4114 Datasheet, PDF (31/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
7.0 APPLICATION NOTES
7.1 POWER AND GROUND CONNECTIONS
The GC4114 chip is a very high performance chip which requires solid power and ground connections to
avoid noise on the V_CC and GND pins. If possible the GC4114 chip should be mounted on a circuit board with
dedicated power and ground planes and with at least two decoupling capacitors (0.01 and 0.1 µf) adjacent to each
GC4114 chip. If dedicated power and ground planes are not possible, then the user should place decoupling
capacitors adjacent to each V_CC and GND pair.
IMPORTANT
The GC4114 chip may not operate properly if these power and ground guidelines are violated.
7.2 STATIC SENSITIVE DEVICE
The GC4114 chip is fabricated in a high performance CMOS process which is sensitive to the high voltage
transients caused by static electricity. These parts can be permanently damaged by static electricity and should only
be handled in static free environments.
7.3 SYNCHRONIZING MULTIPLE GC4114 CHIPS
A system containing two or more GC4114 chips will need to be synchronized if coherent operation is
desired. To synchronize multiple GC4114 chips connect all of the sync input pins together so they can be driven by
a common sync strobe. The common sync strobe can be from an external source, or can be the sync output from
one of the chips. If the sync output from one of the chips is used, then the user can choose to output a one shot sync
pulse from that chip, or the terminal count from the chip’s sync counter. If the terminal count is used, then the sync
cycle must be a multiple of 8N and the FLUSH (Address 12), NCO_SYNC and DITHER_SYNC (Addresses 8, 9, 10
and 11) sync control bits must be set to “never” (see Table 1) after initial synchronization.
See Figure 10 in Section 7.5 for an example configuration of multiple chips and see Section 7.9 for a
description of how to periodically synchronize multiple chips.
7.4 THERMAL MANAGEMENT
The junction temperature must be kept below 125 °C for reliable operation. The chip’s power dissipation
should be calculated using the equation for supply current in Section 6.5 and then the chip’s junction temperature
can be calculated using the package’s thermal conductivity shown in Section 6.3. At full rate operation (F_CK=70MHz)
the power is 1.44 Watts and the junction to ambient rise is 32 degrees per Watt for the plastic package. This
represents a rise of 46 degrees over ambient. This means that under these conditions the ambient temperature has
to be less than 79 °C. Air flow will decrease the thermal resistance by 10% to 40%, allowing ambient temperatures
between 84°C and 97 °C. Increasing the decimation ratio (N) or decreasing the number of active channels (A) will
also allow a higher ambient temperature operation.
Texas Instruments Inc.
- 27 -
MAY 22, 2000
This document contains information which may be changed at any time without notice