GC4114 Datasheet, PDF (13/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
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DATA SHEET REV 1.0
No Dithering
Figure 8. Example NCO Output
With Dithering
3.5 THE OVERALL INTERPOLATION FILTER RESPONSE
The image rejection of the up-convert channel is equal to the stop band rejection of the overall interpolation
filter response. The overall response is obtained by superimposing the interpolated responses of the PFIR and CFIR
filters onto the CIC filter response. The overall response is shown in Figure 9. Figure 9a shows the overall response
using the default PFIR coefficients. Figure 9b shows the response using a root-raised-cosine PFIR coefficient set.
Figure 9c shows the response when using the 2x mode root-raised cosine PFIR coefficient set.
(a) Internal Coefficients
(b) RRC (Alpha=0.35) Filter
(c) RRC (Alpha=0.35) At 2X
Figure 9. Overall Filter Response
3.6 THE SUM TREE
The four up-convert channel outputs are summed together, scaled down by powers of two and then added
to an external sum input. The sum tree output is rounded to 8, 10, 12, 14 or 16 bits and output from the chip. The
sum of the four channels within the chip can be scaled down by powers of two in order to prevent saturation when
channels from multiple chips are summed together. The scale factor is equal to 2^-SUM_SCALE, where SUM_SCALE
is 0,1,2 or 3 (See Section 5.9). Overflows in the sum tree are saturated to plus or minus full scale.
The latency from IN[0:15] to OUT[[0:15] is seven clock cycles. The chip will optionally invert the MSB output
(OUT15) from the chip in order to drive offset binary format digital to analog converters (DACs)
Texas Instruments Inc.
-9-
MAY 22, 2000
This document contains information which may be changed at any time without notice