GC4114 Datasheet, PDF (42/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
interface is working, then the output should be the same as was recorded. The expected value is 0x9090 for power
of 2 interpolation ratios. For the QPSK 1X mode described in Section 7.5 with addresses 2, 3 and 4 set to 0x5A,
0x2B and 0x01 respectfully, the output should be 0xA654. The same value is expected for the 2X QPSK mode
where addresses 2, 3, and 4 are 0x5D, 0x57 and 0x02 respectfully.
7.9 PERIODIC SYNC MODE
The configuration shown in Figure 10 allows all four chips to be synchronized to the master chip’s SO
output. This connection allows the system to be periodically synchronized by the master chip using its internal
counter. By periodically synchronizing the system the user can insure that all of the chips will return to being in sync,
even if one chip is thrown out of sync by noise, alpha particles or other factors such as lightning.
In the periodic sync mode the chips are configured so that the interpolation control counter (bits 0 and 1 of
address 0) is synchronized by SI, but all other syncs are set to ignore SI (set to “never” in Table 1). The internal
counter registers (addresses 6 and 7) should be set to count in cycles equal to multiples of the interpolation factor
N. The suggested counter setting is to set CNT equal to INT (See Sections 5.4 and 5.6). This will result in a periodic
sync every 128N clocks (every 32 complex inputs). The sync output control (bits 4 and 5 of address 0) should be
set to 2 (TC), and the USE_ONESHOT mode should be turned off. The FLUSH (address 12), NCO_SYNC and
DITHER_SYNC (addresses 8, 9, 10, and 11) must be set to never.
The suggested initialization procedure for using the periodic sync mode is to configure the chips in the
normal mode (see for example Tables 10 and 11), send the one shot pulse, wait 8 clock cycles for the chips to
become synchronized, set up the periodic sync mode for all registers except address 0 (also set the
FILTER_SELECT bit if necessary in address 1), and then put address 0 in the periodic sync mode. Table 18 shows
the necessary settings.
Table 18: Periodic Sync Initialization Procedure
Control
Address
Initial Normal Mode
Settings in all Chips
Generate One Shot in
Chip U0 only
Wait 8 clocks, Then Change
Syncs in all chips to:
Then Change chip U0
To the Periodic Mode
00 (HEX)
65
E5
65
21
01
00¹
02²
02
46³
03
INT
04
05
01⁴
06
INT
07
08
5F
0F
09
5F
0F
0A
5F
0F
0B
5F
0F
0C
55
00
0D
0A, 02, 42³
1.Configure REQ_POL, REQ_WIDTH and REAL as necessary.
2. Set FILTER_SELECT as necessary.
3. Set to the appropriate SCALE, BIG_SCALE and AUTO_FLUSH values.
4. Set as necessary for the desired input format.
3. For example, chip U0 uses 0A for SUM_CLR, U1 and U2 use 02 for sum I/O mode, and U3 uses 42 for round to 12 bits.
Texas Instruments Inc.
- 38 -
MAY 22, 2000
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