GC4114 Datasheet, PDF (24/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
5.10 STATUS CONTROL REGISTER
This register contains miscellaneous control and status information.
ADDRESS 14: Status Control Register, suggested default = 0x08
BIT
TYPE
NAME
DESCRIPTION
0 LSB
R/W
INPUT_READY
The user sets this bit after loading the input registers. The chip clears
this bit when the values have been read and it is time to load new
ones.
1
R/W
MISSED
The chip sets this bit If the user has not set the INPUT_READY bit
before the chip reads the input registers. This bit high indicates that
an error has occurred.
2
R/W
PD_CLOCK_OFF
Power_Down modes 0 and 1 normally use a 1 kHz keep alive
clock. This clock is disabled when this bit is high.
3
R/W
EN_DOUBLER
Enables the clock doubling circuit. This bit defaults to low. The
user must set the bit to enable the clock doubler.
4,5
R/W
PAGE
Selects the page mode for control addresses 32 to 63 as follows:
PAGE
MODE
0
Frequency, Phase and Gain
1
Status and Test monitors
2
Filter coefficients 0 to 15
3
Filter coefficients 16 to 31
6,7
R/W
POWER_DOWN
This two bit field controls the power down and keep alive circuit as
follows:
POWER_DOWN
MODE
0
Clock loss detect mode
1
Power down mode
2
Disabled
3
Test
The power_down bits default to 0 (clock loss detect mode) upon power
up.
The INPUT_READY bit is used to tell an external processor when to load new input samples. If desired, the
REQ pin can be used as an interrupt to the external processor (See Section 5.2) to tell the processor when to load
new samples. The user does not need to set the INPUT_READY bit if REQ is used. If INPUT_READY is not set,
however, the MISSED flag will not be valid. NOTE: the parallel input mode assumes the data is being entered as
complex pairs, even when the data is real. To enter real data in the parallel mode, the user must put the real data
into complex pairs, the first sample of each pair in the I-half and the second in the Q-half.
5.11 CHECKSUM REGISTER
The checksum register is a read only register which contains the checksum of the OUT[0:15] data. The
checksum is stored in the checksum register and then starts over again each time the DIAG_SYNC (See Section
5.2) occurs. This is a read only register. For example diagnostic configurations see Section 7.6.
ADDRESS 15: Checksum Register
BIT
TYPE
0-7
R
NAME
CHECKSUM[0:7]
DESCRIPTION
The checksum.
Texas Instruments Inc.
- 20 -
MAY 22, 2000
This document contains information which may be changed at any time without notice