GC4114 Datasheet, PDF (30/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
6.5 AC CHARACTERISTICS
Table 7: AC Characteristics (-40 TO +85^oC Ambient, unless noted)
PARAMETER
SYMBOL
3.1V to 3.5V
MIN MAX
UNITS NOTES
Clock Frequency
Clock low period (Below V_IL)
Clock high period (Above V_IH)
Clock rise and fall times (V_IL to V_IH)
Input setup before CK goes high (IN or SI)
Input hold time after CK goes high
Serial Clock Frequency
Serial Clock low or high period
Serial Data Setup before SCK
Serial Data Hold from SCK
Data output delay from rising edge of CK.
(OUT or SO)
F_CK
Note 5 70
MHz
2, 3
t_CKL
6
ns
1
t_CKH
6
ns
1
t_RF
2
ns
1
t_SU
2
ns
2
t_HD
1
ns
2
F_SCK
0
75
MHz
2,9
t_SCKL/H
5
ns
2,9
t_SSU
2
ns
2,9
t_SHD
2
2,9
t_DLY
2
11
ns
4
Note 1 Note 2
Control Setup before both CE, WR or RD go low
Control hold after CE, WR or RD go high
Control strobe (CE or WR) pulse width (Write operation)
Control output delay CE and RD low to C (Read Operation)
t_CSU
3
t_CHD
3
t_CSPW
30
t_CDLY
45
ns
2, 8, 10
ns
2, 8, 10
ns
2, 8, 10
ns
2, 6, 8,
10
Control tristate delay after CE and RD go high
Quiescent supply current
(V_IN=0 or V_CC, F_CK = 1KHz or POWER_DOWN=1)
Supply current
(F_CK =50MHz, N=8)
t_CZ
I_CCQ
I_CC
10
ns
1
4
mA
1
350
mA
2, 7
Notes:
1. Controlled by design and process and not directly tested. Verified on initial part evaluation.
2. Each part is tested at 85 degrees C for the given specification.
3. The chip may not operate properly at clock frequencies below MIN and above MAX.
4. Output load is 2mA. Delays are measured from the rising edge of the clock to the output level rising above or
Falling below V_CC/2.
5. The minimum clock rate must satisfy F_CK/(4N) > 1KHz, where N is the CIC interpolation ratio.
6.Output load is 2mA.
7.
Current
changes
linearly
with
voltage
and
clock
speed: Icc (MAX)
=


V_---3-C_--.--3-C_{---}


5-^F--0--C--M^{-K--}


1
+
N------7+---8--1---8--^


1---2---1--+-6----A--- _
88
mA
where A is the number of active channels (0 to 4) and N is the CIC interpolation ratio.
8. See timing diagram in Figure 2 and description in Section 3.1.
9. See timing diagram in Figure 3 and description in Section 3.2
10. Not tested for V_UP at 5 volts.
Texas Instruments Inc.
- 26 -
MAY 22, 2000
This document contains information which may be changed at any time without notice