GC4114 Datasheet, PDF (20/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
5.2 INTERPOLATION MODE REGISTER
Registers 1 and 2 control the interpolation modes for the chip. These settings are common to all channels
ADDRESS 1:
Interpolation Mode, suggested default = 0x00
BIT
0 LSB
TYPE
R/W
NAME
REAL
1
R/W
FILTER_SELECT
2
R/W
REQ_POL
3
R/W REQ_WIDTH
4
R/W DIAG
5
R/W SO_OVF_MODE
6,7
R/W DIAG_SYNC
DESCRIPTION
The input samples are real when this bit is set and are up-converted as a single sideband
signal. The input samples are treated as complex when this bit is low. The input rate is
F_CK/4N when this bit is low and is F_CK/2N when this bit is high, where F_CK is the chip’s clock
rate and N is the interpolation setting in registers 3 and 4 (See Section 5.4). If double
sideband real data is to be up-converted, then the complex mode should be used with the
Q-half set to zero.
The user downloaded filter coefficients are used instead of the built in filter coefficients for
the PFIR filter when this bit is set. This bit must be cleared for at least 4N clock cycles before
it is set.
This control bit inverts the polarity of the REQ output. Normally REQ pulses high when a new
sample is requested. REQ will pulse low when REQ_POL is high.
Normally the REQ pin will pulse high for two clock cycles. This control bit forces REQ to be
high for “N/2” clocks. NOTE: the period of the REQ signal is either 4N or 2N clocks,
depending upon whether the REAL_INPUT control bit is low or high in the input mode control
register (See Section 5.5).
Use the diagnostic ramp as the input source for the four channels. The ramp starts at -32768
and counts up to +32768 and starts over again. The ramp increments once every complex
input cycle (every 4N clocks).
When set, the SO bit will go low whenever an overflow occurs in the chip. Bits 6 & 7 of control
register 32 of page 1 must be low to use this mode (see Section 5.14).
The diagnostic ramp is synchronized by the sync selected by these bits according to Table
1. This sync also loads the checksum register.
5.3 INTERPOLATION GAIN REGISTER
Register 2 controls the interpolation gain for the chip. These settings are common to all channels
ADDRESS 2:
Interpolation Gain, suggested default = 0x46
BIT
TYPE NAME
DESCRIPTION
0-3
R/W
SCALE
SCALE ranges from 0 to 15.
4,5
R/W
BIG_SHIFT
BIG_SHIFT equals 0, 1 or 2.
6
R/W
AUTO_FLUSH
The chip will automatically flush a channel if instability in the channel’s CIC filter is detected
and this bit is set.
7
R/W
MSB_INVERT
Inverts the MSB of the output data (OUT15) for use with offset binary DACs.
The CIC filter has a gain which is equal to N³. To remove this gain the CIC outputs are shifted down by
(3+SCALE+12*BIG_SHIFT) bits and then rounded to 16 bits before they are sent to the mixer circuit. The value
chosen for BIG_SHIFT must also satisfy: 2^{(12*BIG_SHIFT+18)} ≥ N³. Overflows due to improper gain settings will go
undetected if this relationship is violated. This restriction means that BIG_SHIFT = 0 for N between 8 and 64,
BIG_SHIFT = 1 for N between 65 and 1024, and BIG_SHIFT = 2 for N between 1025 and 16384.
Texas Instruments Inc.
- 16 -
MAY 22, 2000
This document contains information which may be changed at any time without notice