GC4114 Datasheet, PDF (8/45 Pages) Texas Instruments – QUAD TRANSMIT CHIP

GC4114 QUAD TRANSMIT CHIP
DATA SHEET REV 1.0
real word is placed in the upper 16 bits of the 32 bits. Real samples can also be entered in the complex input mode
by alternately placing samples in the I and Q halves of the complex input words. The data request signal (REQ) is
output from the chip to identify when the GC4114 is ready for another serial input sample.
The bit serial inputs use the format shown in Figure 3:
SCK
SFS
SIN
T_SU
T_HD
(must go low before next transfer)
T_SU
T_HD
I15
I14
I13
I3
I2
I1
I0
(a) 16 BIT MODE, ONE OR MORE CLOCKS BETWEEN TRANSFERS
SCK
SFS
SIN
I15
I14
I13
I3
I2
I1
(b) 16 BIT MODE, BACK TO BACK TRANSFER
I0
Q15
SCK
SFS
SIN
(SFS occurs once at beginning of the 32 bit transfer)
I15
I14
I13
I3
I2
I1
I0
Q15
(c) 32 BIT “PACKED” MODE
Figure 3. Serial Input Formats
Figure 3a shows the standard input mode (PACKED in the input control register is low). The user provides
a bit serial clock (SCK), a frame strobe (SFS) and a data bit line (SIN). The chip clocks SFS and SIN into the chip
on the rising edge of SCK (or falling edge if the SCK_POL bit in the input control register is set). The user sends a
16 bit serial input word to the GC4114 by setting SFS high (or low if SFS_POL in the input control register is set) for
at least one SCK clock cycle, and then transmitting the data, MSB first, on the next 16 SCK clocks. The user must
set SFS low at least one SCK clock cycle before the next serial transfer. The data can be transmitted “back to back”
as shown in Figure 3b as long as the SFS signal toggles low and then high as shown. If the PACKED control bit is
high, then the I and Q samples are sent as a single 32 bit word with only one SFS strobe as shown in Figure 3c.
The GC4114 input interface sends a “new sample request” strobe (REQ) when a new input sample is
required for the up-converter channels. The input sample rate is F_S=F_CK/2N for real inputs and F_S=F_CK/4N for
complex inputs, where F_CK is the chip’s clock rate and N is the interpolation ratio in the CIC filter which varies from
8 to 16,384 (See Section 5.4). This means that the REQ strobe will be output from the chip every 2N clocks (CK,
not SCK) in the real mode or every 4N clocks in the complex mode. The pulse width of the REQ strobe can be
specified by the user to be either 2 clocks (CK) wide or N/2 clocks wide. The polarity of REQ is user programmable.
The REQ strobe is typically used as an interrupt to an external device to tell it to send another input sample. The
GC4114 chip must receive the last data bit at least one bit clock (SCK) period before the next REQ strobe.
If the serial interface timing is tight, i.e., the serial bit rate is so slow that the serial frames barely fit between
REQ strobes, then the bit serial transfer can start up to 7 bit clocks before the REQ strobe. This means that the
frame sync can be sent up to 7 bit clocks before REQ.
Texas Instruments Inc.
-4-
MAY 22, 2000
This document contains information which may be changed at any time without notice