CC430F6147_15 Datasheet, PDF (9/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
RGZ PACKAGE
(TOP VIEW)
P2.2/PM_TA1CCR1A/CB2
P2.1/PM_TA1CCR0A/CB1
P2.0/PM_CBOUT1/PM_TA1CLK/CB0
P1.7/PM_UCA0CLK/PM_UCB0STE
P1.6/PM_UCA0TXD/PM_UCA0SIMO
P1.5/PM_UCA0RXD/PM_UCA0SOMI
VCORE
DVCC
P1.4/PM_UCB0CLK/PM_UCA0STE
P1.3/PM_UCB0SIMO/PM_UCB0SDA
P1.2/PM_UCB0SOMI/PM_UCB0SCL
P1.1/PM_RFGDO2
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
CC430F512x
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
R_BIAS
AVCC_RF
AVCC_RF
RF_N
RF_P
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
VSS
Exposed die
attached pad
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. Pinout shows only the default mapping.
See Table 10 for details.
Copyright © 2012–2013, Texas Instruments Incorporated
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