CC430F6147_15 Datasheet, PDF (5/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
RGC PACKAGE
(TOP VIEW)
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
LCDCAP/R33
COM0
P5.7/COM1/S26
P5.6/COM2/S25
P5.5/COM3/S24
P5.4/S23
VCORE
DVCC
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
P1.1/PM_RFGDO2/S19
P1.0/PM_RFGDO0/S18
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
CC430F614x
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
R_BIAS
AVCC_RF
AVCC_RF
RF_N
RF_P
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
P5.2/S0
P5.3/S1
P4.0/S2
VSS
Exposed die
attached pad
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. Pinout shows only the default mapping.
See Table 10 for details.
CAUTION: LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2012–2013, Texas Instruments Incorporated
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