CC430F6147_15 Datasheet, PDF (54/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
www.ti.com
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
SVSLE = 0, PMMCOREV = 2
0
I_(SVSL)
SVS_L current consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
t_pd(SVSL) SVS_L propagation delay
t_(SVSL)
SVS_L on or off delay time
SVSLE = 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0 → 1, dV_CORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 0 → 1, dV_CORE/dt = 1 mV/µs, SVSLFP = 0
2.5
20
12.5
100
MAX
UNIT
nA
nA
µA
µs
µs
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
SVMLE = 0, PMMCOREV = 2
0
I_(SVML)
SVM_L current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
t_pd(SVML)
t_(SVML)
SVM_L propagation delay
SVM_L on or off delay time
SVMLE = 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 → 1, dV_CORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 0 → 1, dV_CORE/dt = 1 mV/µs, SVMLFP = 0
2.5
20
12.5
100
MAX
UNIT
nA
nA
µA
µs
µs
Wake-up From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
t_WAKE-UP-
FAST
Wake-up time from LPM2, LPM3, or
LPM4 to active mode⁽¹⁾
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
f_MCLK ≥ 4.0 MHz
f_MCLK < 4.0 MHz
t_WAKE-UP-
SLOW
t_WAKE-UP-
LPM5
t_WAKE-UP-
RESET
Wake-up time from LPM2, LPM3 or
LPM4 to active mode⁽²⁾
Wake-up time from LPMx.5 to active
mode ⁽³⁾
Wake-up time from RST or BOR
event to active mode⁽³⁾
PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3),
SVSLFP = 0
TYP MAX UNIT
5
µs
6
150 165 µs
2 3 ms
2 3 ms
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low-side supervisor (SVS_L) and low side monitor (SVM_L). Fastest wakeup times are possible with SVS_Land SVM_L in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_L while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family
User's Guide (SLAU259).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low-side supervisor (SVS_L) and low side monitor (SVM_L). In this case, the SVS_Land SVM_L are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_L while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family User's Guide (SLAU259).
(3) This value represents the time from the wakeup event to the reset vector execution.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK,
f_TA
Timer_A input clock frequency
External: TACLK,
Duty cycle = 50% ± 10%
V_CC
1.8 V,
3.0 V
MIN TYP
t_TA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
1.8 V,
3.0 V
20
MAX UNIT
25 MHz
ns
54
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