CC430F6147_15 Datasheet, PDF (36/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
Table 42. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
USCI control 1
USCI control 0
USCI baud rate 0
USCI baud rate 1
USCI modulation control
USCI status
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
REGISTER
UCA0CTL1
00h
UCA0CTL0
01h
UCA0BR0
06h
UCA0BR1
07h
UCA0MCTL
08h
UCA0STAT
0Ah
UCA0RXBUF
0Ch
UCA0TXBUF
0Eh
UCA0ABCTL
10h
UCA0IRTCTL
12h
UCA0IRRCTL
13h
UCA0IE
1Ch
UCA0IFG
1Dh
UCA0IV
1Eh
www.ti.com
OFFSET
Table 43. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
REGISTER
UCB0CTL1
UCB0CTL0
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
UCB0IFG
UCB0IV
OFFSET
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
Table 44. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
ADC10_A Control register 0
ADC10_A Control register 1
ADC10_A Control register 2
ADC10_A Window Comparator Low Threshold
ADC10_A Window Comparator High Threshold
ADC10_A Memory Control Register 0
ADC10_A Conversion Memory Register
ADC10_A Interrupt Enable
ADC10_A Interrupt Flags
ADC10_A Interrupt Vector Word
REGISTER
ADC10CTL0
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10HI
ADC10MCTL0
ADC10MEM0
ADC10IE
ADC10IGH
ADC10IV
OFFSET
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
36
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated