CC430F6147_15 Datasheet, PDF (59/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 21)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
f_SCL
t_HD,STA
t_SU,STA
t_HD,DAT
t_SU,DAT
t_SU,STO
t_SP
SCL clock frequency
Hold time (repeated) START
Setup time for a repeated START
Data hold time
Data setup time
Setup time for STOP
Pulse duration of spikes suppressed by input
filter
f_SCL ≤ 100 kHz
f_SCL > 100 kHz
f_SCL ≤ 100 kHz
f_SCL > 100 kHz
f_SCL ≤ 100 kHz
f_SCL > 100 kHz
2.2 V, 3 V
0
4.0
2.2 V, 3 V
0.6
4.7
2.2 V, 3 V
0.6
2.2 V, 3 V
0
2.2 V, 3 V 250
4.0
2.2 V, 3 V
0.6
2.2 V
50
3V
50
400 kHz
µs
µs
ns
ns
µs
600
ns
600
SDA
t_HD,STA
t_SU,STA
t_HD,STA
t_BUF
t_LOW
t_HIGH
t_SP
SCL
t_HD,DAT
t_SU,DAT
Figure 21. I2C Mode Timing
t_SU,STO
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