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| CC430F6147_15 Datasheet, PDF (26/118 Pages) Texas Instruments – MSP430 SoC With RF Core | |||
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CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A â NOVEMBER 2012 â REVISED FEBRUARY 2013
www.ti.com
TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 14. TA0 Signal Connections
DEVICE INPUT SIGNAL MODULE INPUT NAME
PM_TA0CLK
ACLK (internal)
SMCLK (internal)
RFCLK/192 (1)
PM_TA0CCR0A
DVSS
DVSS
DVCC
PM_TA0CCR1A
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
VCC
CCI1A
CBOUT (internal)
CCI1B
DVSS
DVCC
PM_TA0CCR2A
ACLK (internal)
DVSS
DVCC
PM_TA0CCR3A
GDO1 from radio
(internal)
DVSS
DVCC
PM_TA0CCR4A
GDO2 from radio
(internal)
DVSS
DVCC
GND
VCC
CCI2A
CCI2B
GND
VCC
CCI3A
CCI3B
GND
VCC
CCI4A
CCI4B
GND
VCC
MODULE BLOCK
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
MODULE OUTPUT
SIGNAL
NA
TA0
TA1
TA2
TA3
TA4
DEVICE OUTPUT
SIGNAL
PM_TA0CCR0A
PM_TA0CCR1A
ADC10 (internal)(2)
ADC10SHSx = {1}
PM_TA0CCR2A
PM_TA0CCR3A
PM_TA0CCR4A
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
(2) Only on CC430F614x and CC430F514x.
26
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