CC430F6147_15 Datasheet, PDF(17/118 Page) Texas Instruments

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CC430F6147_15 Datasheet, PDF (17/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F614x

CC430F514x

CC430F512x

SLAS555A â NOVEMBER 2012 â REVISED FEBRUARY 2013

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 5. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE

INTERRUPT FLAG

System Reset

Power-Up

External Reset

Watchdog Timeout, Password

Violation

Flash Memory Password Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

User NMI

NMI

Oscillator Fault

Flash Memory Access Violation

Comparator_B

Watchdog Interval Timer Mode

USCI_A0 Receive or Transmit

USCI_B0 Receive or Transmit

ADC10_A

(Reserved on CC430F512x)

TA0

RF1A CC1101-based Radio

DMA

TA1

I/O Port P1

I/O Port P2

LCD_B

(Reserved on CC430F514x and

CC430F512x)

RTC_D

AES

WDTIFG, KEYV (SYSRSTIV)(1)(2)

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

JMBOUTIFG (SYSSNIV)(1)(3)

NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1)(3)

Comparator_B Interrupt Flags (CBIV)(1)

WDTIFG

UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)

UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt

Flags (UCB0IV)(1)

ADC10IFG0, ADC10INIFG, ADC10LOIFG,

ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG

(ADC10IV) (1)

TA0CCR0 CCIFG0

TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,

TA0IFG (TA0IV)(1)

Radio Interface Interrupt Flags (RF1AIFIV)

Radio Core Interrupt Flags (RF1AIV)

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)

TA1CCR0 CCIFG0

TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,

TA1IFG (TA1IV)(1)

P1IFG.0 to P1IFG.7 (P1IV)(1)

P2IFG.0 to P2IFG.7 (P2IV)(1)

LCD_B Interrupt Flags (LCDBIV)(1)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)

AESRDYIFG

Reserved

Reserved (4)

SYSTEM

INTERRUPT

Reset

(Non)maskable

Maskable

WORD

ADDRESS

PRIORITY

0FFFEh

63, highest

0FFFCh

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

0FFDEh

0FFDCh

0FFDAh

0FFD8h

â®

0FF80h

â®

0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.

(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

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