CC430F6147_15 Datasheet, PDF (39/118 Pages) Texas Instruments – MSP430 SoC With RF Core

www.ti.com
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to V_SS
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS)⁽²⁾
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS⁽²⁾
-0.3 V to 4.1 V
-0.3 V to (V_CC + 0.3 V),
4.1 V Maximum
-0.3 V to 2.0 V
Input RF level at pins RF_P and RF_N
10 dBm
Diode current at any device terminal
Storage temperature range⁽³⁾, T_stg
Maximum junction temperature, T_J
±2 mA
-55°C to 150°C
95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics CC430F51xx
θ_JA Junction-to-ambient thermal resistance, still air
Low-K board
High-K board
48 QFN (RGZ)
48 QFN (RGZ)
98°C/W
28°C/W
Thermal Packaging Characteristics CC430F61xx
θ_JA Junction-to-ambient thermal resistance, still air
Low-K board
High-K board
64 QFN (RGC)
64 QFN (RGC)
83°C/W
26°C/W
Recommended Operating Conditions
Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)
V_CC
V_CC
V_CC
V_SS
T_A
T_J
C_VCORE
C_VCORE
C_DVCC
Supply voltage range applied at all DVCC and AVCC
pins⁽¹⁾⁽²⁾ during program execution and flash
programming with PMM default settings. Radio is not
operational with PMMCOREVx = 0, 1.⁽³⁾
Supply voltage range applied at all DVCC and AVCC
pins⁽¹⁾⁽²⁾ during program execution, flash programming
and radio operation with PMM default settings.⁽³⁾
Supply voltage range applied at all DVCC and AVCC
pins⁽¹⁾⁽²⁾ during program execution, flash programming
and radio operation with PMMCOREVx = 2, high-side
SVS level lowered (SVSHRVLx = SVSHRRRLx = 1) or
high-side SVS disabled (SVSHE = 0).⁽⁴⁾⁽³⁾
Supply voltage applied at the exposed die attach VSS
and AVSS pin
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE
Reduced capacitor at VCORE
Recommended capacitor at DVCC
PMMCOREVx = 0
(default after POR)
PMMCOREVx = 1
PMMCOREVx = 2
PMMCOREVx = 3
PMMCOREVx = 2,
SVSHRVLx = SVSHRRRLx = 1
or SVSHE = 0
f_SYSTEM ≤ 16 MHz,
PMMCOREVx ≤ 2, V_CC ≥ 2.2 V
MIN NOM MAX UNIT
1.8
3.6 V
2.0
3.6 V
2.2
3.6 V
2.4
3.6 V
2.0
3.6 V
0
-40
-40
470
100
4.7
V
85 °C
85 °C
nF
nF
µF
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation but the core voltage
still stays within its limits and is still supervised by the low-side SVS to ensure reliable operation.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
39