CC430F6147_15 Datasheet, PDF (30/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
Table 17. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
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OFFSET
Table 18. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
PMM Control 0
PMM control 1
SVS high side control
SVS low side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
REGISTER
PMMCTL0
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
PMMIE
PM5CTL0
OFFSET
00h
02h
04h
06h
0Ch
0Eh
10h
Flash control 1
Flash control 3
Flash control 4
Table 19. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
FCTL1
FCTL3
FCTL4
OFFSET
00h
04h
06h
Table 20. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
CRC data input
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
REGISTER
CRC16DI
CRCDIRB
CRCINIRES
CRCRESR
OFFSET
00h
02h
04h
06h
RAM control 0
Table 21. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
RCCTL0
OFFSET
00h
Watchdog timer control
Table 22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
OFFSET
00h
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
Table 23. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCSCTL0
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
30
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