CC430F6147_15 Datasheet, PDF (62/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
www.ti.com
10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
AV_CC
V_(Ax)
PARAMETER
TEST CONDITIONS
Analog supply voltage
Analog input voltage range⁽²⁾
AV_CC and DV_CC are connected together,
AV_SS and DV_SS are connected together,
V_(AVSS) = V_(DVSS) = 0 V
All ADC10_A pins: P1.0 to P1.5, P3.6, P3.7
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal. REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
and reference buffer off.
ADC10SREF = 00
V_CC
2.2 V
3V
MIN TYP MAX UNIT
1.8
3.6 V
AV_CC V
70 105
µA
80 115
Operating supply current into f_ADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
AVCC terminal. REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3V
on, reference buffer on.
ADC10SREF = 01
I_{ADC10_A Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,}
AVCC terminal. REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3V
off, reference buffer on.
ADC10SREF = 10, VEREF = 2.5 V
130 185 µA
120 170 µA
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal. REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
3V
off, reference buffer off.
ADC10SREF = 11, VEREF = 2.5 V
85 120 µA
C_I
Input capacitance
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad.
2.2 V
3.5
pF
R_I
Input MUX ON resistance
AV_CC > 2.0 V, 0 V ≤ V_Ax ≤ AV_CC
1.8 V < AV_CC < 2.0 V, 0 V ≤ V_Ax ≤ AV_CC
36
kΩ
96
(1) The leakage current is defined in the leakage current table with P2.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range V_R+ to V_R-for valid conversion results. The external
reference voltage requires decoupling capacitors. See ⁽⁾.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f_ADC10CLK
TEST CONDITIONS
For specified performance of ADC10_A linearity
parameters
V_CC
2.2 V, 3 V
MIN TYP
0.45
5
f_ADC10OSC
Internal ADC10_A
oscillator ⁽¹⁾
ADC10DIV = 0, f_ADC10CLK = f_ADC10OSC
2.2 V, 3 V
4.2 4.8
t_CONVERT Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK cycles,
10-bit mode, f_ADC10OSC = 4 MHz to 5 MHz
2.2 V, 3 V
2.4
External f_ADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSEL ≠ 0
(2)_tADC10ON
Turn on settling time of
the ADC
t_Sample
Sampling time
See ⁽³⁾
R_S = 1000 Ω, R_I = 96 kΩ, C_I = 3.5 pF⁽⁴⁾
R_S = 1000 Ω, R_I = 36 kΩ, C_I = 3.5 pF⁽⁴⁾
1.8 V
3
3V
1
MAX UNIT
5.5 MHz
5.4 MHz
3.0
µs
100 ns
µs
µs
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) 12 × ADC10DIV × 1/f_ADC10CLK
(3) The condition is that the error in a conversion started after t_ADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(4) Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB
62
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated