CC430F6147_15 Datasheet, PDF (67/118 Pages) Texas Instruments – MSP430 SoC With RF Core

www.ti.com
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
DV_{CC(PGM/ERASE)} Program or erase supply voltage
I_PGM
Average supply current from DVCC during program
I_ERASE
Average supply current from DVCC during erase
I_MERASE, I_BANK
Average supply current from DVCC during mass erase or bank
erase
t_CPT
Cumulative program time⁽¹⁾
Program and erase endurance
1.8
3
2
2
10⁴
10⁵
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time⁽²⁾
Block program time for first byte or word⁽²⁾
T_J = 25°C
100
64
49
t_{Block, 1-(N-1)}
Block program time for each additional byte or word, except for last
byte or word⁽²⁾
37
t_{Block, N}
Block program time for last byte or word⁽²⁾
55
t_Erase
Erase time for segment erase, mass erase, and bank erase when
available ⁽²⁾
23
f_MCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
MAX UNIT
3.6 V
5 mA
6.5 mA
6.5 mA
16 ms
cycles
years
85 µs
65 µs
49 µs
73 µs
32 ms
1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
f_SBW
t_SBW,Low
t_{SBW, En}
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
0.025
t_SBW,Rst
f_TCK
Spy-Bi-Wire return to normal operation time
TCK input frequency - 4-wire JTAG⁽²⁾
15
2.2 V
0
3V
0
R_internal
Internal pull-down resistance on TEST
2.2 V, 3 V
45
60
MAX UNIT
20 MHz
15 µs
1 µs
100 µs
5 MHz
10 MHz
80 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the minimum t_SBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
67