GC1115_06 Datasheet, PDF (79/82 Pages) Texas Instruments – Crest Factor Reduction Processor

www.ti.com
DATE
JUN 06
REV
C
OCT 05
B
JUL 05
A
FEB 04
*
GC1115
Revision History
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
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SECTION
DESCRIPTION
Latency
Added an equation to calculate the latency of the device.
Device Information
Corrected OUT_A and OUT_B pin labeling.
Terminal Information Corrected OUT_A and OUT_B pin labeling.
Operating Modes
Valid decimation values are 1 and 2.
Microprocessor I/F
Clarified 2-pin and 3-pin operation.
GC1115 Power
New section on power consumption.
Recommended
Added max. power consumption specification.
Operating Conditions
Switching
Characteristics
Updated tperiod, tout_hd, tout_dly.
Figure 15
Updated tout_hd and tout_dly diagram.
Terminal Functions
WR_ is used in two-pin mode to distinguish between read and write.
Terminal Functions
RD_ is grounded in two-pin mode.
Changed VSS: G7-G11 to G6-G11.
Changed VSS: L7-L11 to L6-L11.
Figure 16
Removed extraneous text.
GC1115 JTAG
New section on JTAG usage.
Functional Block
Diagram
Changed PLL1 to PLL_CORE and PLL2 to PLL_TX.
Table 1
Updated cEVM and PCDE performance measurements.
Table 4
Corrected PLL_MULT column entries.
Table 15
Table was double-labeled (“Table 15. Table 17.”). Also added a column for
hex values as well as decimal values.
CANCEL_DATA
Cancel coefficients are 12 bits wide, not 16 bits wide.
DELAY_MASK
Changed hex address 0x12 to 0x14 (20 decimal).
Tables
Updated various table values (Dissipation, Capacitance, etc.)
Switching
Characteristics
Updated various switching and timing parameters.
Timing Parameter
Information
Removed Figure 15, Read Cycle - Normal Mode
Application Information Added a “Recommended Board Bring-up Procedures” section.
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Original version
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