GC1115_06 Datasheet, PDF (26/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
www.ti.com
Figure 10. Minimum Phase Cancel Pulse Impulse Response, CANCEL_DELAY = 7
Software Timer
The GC1115 provides a flexible, user-controlled software timer that can serve as a programmable
synchronization source. The timer is controlled through the TIMER_SYNC register, which allows users to select
the event that triggers the timer. Before enabling the timer to start (via the TIMER_CTL register), the user
specifies a timer period using the TIMER_HI_RST and TIMER_LO_RST registers. The timer is decremented
with each internal clock edge (normally at a frequency of 4 x IN_CLK). When the TIMER_SYNC event occurs,
the timer copies the 32-bit values contained in TIMER_HI_RST and TIMER_LO_RST into a GC1115-internal
32-bit timer register. This 32-bit timer is then decremented with each internal chip clock (normally chip clock = 4
x IN_CLK). When the timer reaches zero, the timer is re-loaded from TIMER_HI_RST and TIMER_LO_RST
(periodic timer event), or the timer is disabled (for one-time timer events). Bit 15 of the TIMER_SYNC register
determines the timer mode (periodic or one-time).
The microprocessor or DSP can be interrupted when the timer expires by setting bit 4 of INT_MASK. It is
expected that software-initiated timer start operation will most often be used in one-time mode (and not periodic
mode), thus giving the microprocessor or DSP time to monitor a GC1115 event, such as reading the snapshot
RAM contents.
Signal Generator and CRC Generator
The GC1115 contains a simple signal generator that can be used to drive the GC1115 PDC stages. The signal
generator capability is useful when debugging a board containing a GC1115, or to debug the GC1115 itself.
When enabled, the signal generator output drives the input of PDC Stage 1. The signal generator can be
configured to generate one of several types of signals:
• A DC level
• A sawtooth waveform
• A pseudo-LFSR waveform with PAR of approximately 10 dB
The signal generator is configured using the SIG_GEN_CTL, SIG_GEN_BASE, and SIG_GEN_INC registers.
The signal generator period is determined by SIG_GEN_CTL, SIG_GEN_BASE, SIG_GEN_INC, and
SIG_GEN_SYNC registers. In LFSR mode, the LFSR generator and the CRC generators are reset whenever a
SIG_GEN_SYNC trigger occurs. Because the GC1115 pipeline must contain predictable information, the
minimum SIG_GEN_SYNC period should be at least 1000 IN_CLK periods.
The GC1115 also contains a cyclic redundancy check (CRC) generator. The CRC generator receives its input
from the output of PDC Stage 4. The CRC generator is enabled whenever the signal generator is enabled. The
CRC generator can also be fed using user-provided data on Input Port A and B, and by setting SIG_GEN_CTL
to 0x3. CRC generation using sawtooth or LFSR data provides a predictable, periodic way to determine proper
internal GC1115 operation, independent of a user-provided input sequence. Note that the LFSR sequence is not
bandlimited, but the distribution of its magnitudes is Gaussian.
26
Submit Documentation Feedback