GC1115_06 Datasheet, PDF (68/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
www.ti.com
SWITCHING CHARACTERISTICS (continued)
PARAMETER
JTAG:
tjt_hd
JTAG input (TDI or TMS) hold time after TCK goes high
tjt_dly
JTAG output (TDO) delay from falling edge of TCK
tjt_oh
JTAG output (TDO) hold time from falling edge of TCK
FUNC DATAPATH:
tin_duty_cycle Clock duty cycle
tperiod
Clock period
1:4x ⁽¹⁾
1:2, 1:x⁽¹⁾
tin_ckh
Clock high time
1:4x ⁽¹⁾
1:2, 1:x⁽¹⁾
tin_ckl
Clock low time
1:4x ⁽²⁾
1:2, 1:x⁽²⁾
tin_su
Input setup before clock goes high
tin_hd
Input hold time after clock goes high
tout_dly
Output delay from rising edge of clock
tout_hd
Output hold time from rising edge of clock
MPUREG 2 WIRE MODE:
tup_cenh
CE_N high time
tup_cenl
CE_N low time
tup_a_su
Address setup time before read or write
tup_a_hd
Address hold time after read or write
tup_rc_su
Control setup time before read
tup_wc_su
Control setup time before write
tup_rc_hd
Control hold after read
tup_wc_hd
Control hold after write
tup_wd_su
Control data setup before read or write
tup_wd_hd
Control data hold after read or write
tup_dly
Control ouput delay CE low and A stable to C(read operation)
MUPRAM 2 WIRE MODE:
tup_cenh
CE_N high time
tup_cenl ⁽³⁾
CE_N low time
tup_a_su
Address setup time before read or write
tup_a_hd
Address hold time after read or write
tup_rc_su
Control setup time before read
tup_wc_su
Control setup time before write
tup_rc_hd
Control hold after read
tup_wc_hd
Control hold after write
tup_wd_su
Control data setup before read or write
tup_wd_hd
Control data hold after read or write
tup_dly ⁽³⁾
Control output delay CE low and A stable to C(read operation)
MIN
MAX UNIT
4
ns
4
ns
1 ns
43.75% 56.25%
12.5
ns
7.7
ns
5.47
7.03 ns
3.37
4.33 ns
5.47
7.03 ns
3.37
4.33 ns
0.5
ns
1.0
ns
2.4
ns
0.2 ns
4
ns
7
ns
6
ns
3
ns
6
ns
2
ns
0
ns
2
ns
2
ns
3
ns
6.5 ns
3
ns
2 × tcore
ns
7
ns
3.5
ns
7
ns
4
ns
0
ns
0
ns
2
ns
3.5
ns
2 × tcore ns
(1) These are for different clocking modes. One clocking mode is identified as (1:4:x) and means the internal clock is 4x the chip's input
clock (IN_CLK) and the transmit clock can be 1x, 2x or 4x IN_CLK's rate. The second clocking mode is (1:2,1:x) and means the internal
clock is 2x or 1x the chip's input clock (IN_CLK) and the transmit clock can be 1x (or 2x if the core clock is 2x) IN_CLK's rate.
(2) These are for different clocking modes. One clocking mode is identified as (1:4:x) and means the internal clock is 4x the chip's input
clock (IN_CLK) and the transmit clock can be 1x, 2x or 4x IN_CLK's rate. The second clocking mode is (1:2,1:x) and means the internal
clock is 2x or 1x the chip's input clock (IN_CLK) and the transmit clock can be 1x (or 2x if the core clock is 2x) IN_CLK's rate.
(3) tup_cenl and tup_dly are a function of tcore, the GC1115 internal clock period. tcore's relationship to IN_CLK is determined by the core
PLL setup (options are 1x, 2x, and 4x multiples of the IN_CLK rate). Under normal operating conditions, the core PLL is set to 4 x
IN_CLK. Under these conditions, the duration of tcore is 1/4 of IN_CLK.
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