GC1115_06 Datasheet, PDF (39/82 Pages) Texas Instruments – Crest Factor Reduction Processor

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GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
MASK_REV
0x6
Type: Read Only Value at RESET: 0x0001 (HW-version dependent)
The MASK_REV register allows the controlling microprocessor or DSP to determine the hardware revision of a
particular GC1115. MASK_REV is useful in determining, via software, which version of the GC1115 is present
on a board or in a system, in the event that different functionality exists in two or more revisions of GC1115
silicon.
BITS
[15:0]
DESCRIPTION
GC1115 mask revision (a 16-bit, non-zero value)
SW_TRIGGER 0x7
Type: Read/Write Value at RESET: 0x0000
The SW_TRIGGER register is a software trigger source that can synchronize one or more of thirteen internal
GC1115 components via software command. If a component’s SYNC register (from Address 0x19 to Address
0x25) selects SW_TRIG as its SYNC source, setting that component’s bit in the SW_TRIGGER register will sync
the component. The GC1115 automatically clears the SW_TRIGGER bits after the trigger occurs.
BITS
0
1
2
3
4
5
6
7
8
9
10
11
12
[15:13]
DESCRIPTION
RCV_SYNC (receive datapath)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
STAGE_SYNC (PDC stage)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
DECIM_SYNC (decimator)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
TIMER_SYNC (SW timer)
0 = no effect, 1 = trigger
DELAY_SYNC (apply CANCEL_DELAY) 0 = no effect, 1 = trigger
CANCEL_SYNC (change cancel coefs)
0 = no effect, 1 = trigger
RESOURCE_SYNC (apply
RESOURCE_CNT)
0 = no effect, 1 = trigger
INTERP_SYNC (sync interp-by-4 block)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
OUTGAIN_SYNC (change outgain)
0 = no effect, 1 = trigger
OUTPIN_SYNC (apply OUT_SYNC)
0 = no effect, 1 = trigger
SIG_GEN_SYNC (signal generator)
0 = no effect, 1 = trigger
SNAP_A_SYNC (Snapshot RAM A)
0 = no effect, 1 = trigger
SNAP_B_SYNC (Snapshot RAM B)
0 = no effect, 1 = trigger
Reserved
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