GC1115_06 Datasheet, PDF (33/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
www.ti.com
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
High-Speed Real Output: Odd/Even Mode
When the output sampling rate exceeds 130 MHz (which may occur when the interp-by-4 block is enabled), the
GC1115 provides a high-speed odd-even output mode. This high-speed output mode requires that the
interp-by-4 block is either in interp-by-2, real output mode, or in interp-by-4, real output mode. The special
high-speed output mode is configured using bits [3:2] of IO_MODE (address 0x9): IO_MODE[3:2] = 11.
NOTE:
GC1115 users should only use the odd/even output mode when the output
pin-toggling rate on OUT_A and OUT_B exceeds 130 MHz.
SYNCHRONIZATION
Figure 12 demonstrates the various registers, input and output pins, and functional blocks that are involved in
synchronizing a variety of functional blocks within the GC1115. GC1115 synchronization involves three
functional areas:
• SYNC sources
• SYNC’d functional blocks, and
• SYNC registers
Refer to Figure 12 for the following discussion.
SYNC Sources
The GC1115 uses two hardware SYNC sources (pins), SYNC_A and SYNC_B. SYNC_A or SYNC_B events are
edge-triggered. Because hardware SYNC sources are active-low signals, the SYNC trigger occurs at the rising
edge, i.e. when SYNC is de-asserted.
The GC1115 has two software SYNC sources: SW_TRIGGER and TIMER. The SW_TRIGGER register
generates a trigger signal for each “1” in the SW_TRIGGER register. The SW_TRIGGER has individual SYNC
bits for each of the functional blocks that can be triggered. The software TIMER is a general-purpose, 32-bit
timer that controls the duration of various events, such as the number of samples captured by a snapshot RAM.
The software TIMER can be configured (via bit 15 of TIMER_SYNC) either to run once or periodically, resetting
to its initial value whenever the timer count reaches zero. Whenever the software timer’s count reaches zero (it
is a count-down timer), it generates a timer SYNC event.
Two other SYNC sources are provided for completeness: NEVER (i.e. the functional block will never be
triggered) and ALWAYS (i.e. the functional block will be updated as soon as its corresponding parameter is
updated). For some functional blocks that are comprised of multiple registers (such as the snapshot RAMs or
the cancellation coefficients), the ALWAYS state is invalid.
NOTE:
Setting a functional block’s SYNC register to NEVER is not the same as disabling the
functional block!
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