GC1115_06 Datasheet, PDF (30/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
Table 14. Interpolate-by-4 Bypass Coefficients
ADDRESS RANGE
0x82 – 0x85
0x86 – 0x89
0x8A – 0x8D
0x8E – 0x91
0x92 – 0x95
0x96 – 0x99
0x9A – 0x9D
0x9E – 0xA1
0xA2 – 0xA5
0xA6 – 0xA9
INTERP-BY-4 COEFFICIENTS
0x8000, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
0, 0, 0, 0
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When the interpolate-by-4 stage is active, the GC1115 requires the interp-by-4 coefficients shown in Table 15:
ADDRESS RANGE
0x82 – 0x85
0x86 – 0x89
0x8A – 0x8D
0x8E – 0x91
0x92 – 0x95
0x96 – 0x99
0x9A – 0x9D
0x9E – 0xA1
0xA2 – 0xA5
0xA6 – 0xA9
Table 15. Interpolate-by-4 2x and 4x Interpolation Coefficients
INTERP-BY-4 COEFFICIENTS (decimal)
0, -4, -21, -35
0, 122, 287, 319
0, -700, -1401, -1372
0, 2519, 4781, 4558
0, -8970, -20028, -29203
-32768, -29203, -20028, -8970
0, 4558, 4781, 2519
0, -1372, -1401, -700
0, 319, 287, 122
0, -35, -21, -4
INTERP-BY-4 COEFFICIENTS (hex)
0x0, 0XFFFC, 0XFFEB, 0XFFDD
0x0, 0x7A, 0x11F, 0x13F
0x0, 0xFD44, 0xFA87, 0xFAA4
0x0, 0x9D7, 0x12AD, 0x11CE
0x0, 0xDCF6, 0xB1C4, 0x8DED
0x8000, 0x8DED, 0xB1C4, 0xDCF6
0x0, 0x11CE, 0x12AD, 0x9D7
0x0, 0xFAA4, 0xFA87, 0xFD44
0x0, 0x13F, , 0x11F, 0x7A
0x0, 0xFFDD, 0xFFEB, 0xFFFC
When the interp-by-4 stage operates in real output mode (i.e. not in complex output mode), it also modulates the
input (baseband) signal to an intermediate frequency. For example, if IN_CLK is 61.44 Msamp/sec, interp-by-2
real mode would raise the sampling rate to 122.88 Msamp/sec (real samples) and the interpolated output signal
would be centered at 122.88 / 4 = 30.72 MHz after the interpolate-by-4 stage.
If the interpolated output sampling rate exceeds 130 Msamp/sec, the output ports must be configured in
odd/even mode. In odd/even mode, successive samples are demultiplexed between OUT_A and OUT_B ports,
effectively lowering the sampling rate on each output port by a factor of 2.
Soft Limiter Operation
NOTE:
Under nearly all operating conditions, the GC1115 Soft Limiter can safely be
bypassed by clearing bit 5 of the CONTROL register at address 0x3. The Soft Limiter
is only required for output PAR levels below 6 dB, when PDC canceler resources
may become continuously busy. However, at PAR levels below 6 dB, the cEVM and
PCDE levels are also likely to be out of spec, even if the Soft Limiter is enabled.
The soft limiter block is the final block in the GC1115 processing chain. The soft limiter provides a final check of
the output samples values after all four PDC stages, can optionally apply a user-specified, multiplicative
attenuation curve to over-threshold samples. When enabled, the soft limiter limits the output samples to the
SOFT_TSQD threshold-squared value. Values above SOFT_TSQD are adjusted over N samples, where N is
specified by the 2 LSBs in SOFT_LENGTH. Valid values for N are 5, 9, 17, or 33. Longer soft limiter lengths
provide more gradual roll-offs and thus provide smaller ACLR increases when the soft limiter is active.
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