GC1115_06 Datasheet, PDF (72/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
www.ti.com
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (Alphabetical Listing)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
A[7:0]
B5, C7, B4, A3, B3,
C6, C1, C2
I Address Bus – Active high inputs
CS
A6
I CHIP SELECT – Active low chip select
D[15:0]
D2, D1, F3, E2, E1,
F2, G3, F1, H3, G2,
G1, H2, H1, J1, J2,
K1
I/O Data Bus - Active high bidirectional I/O
IN_A[17:0]
G16, G15, F16,
G14, F15, E16, F14,
E15, D16, D15, B12,
A13, B11, A12, C9,
I
Input Port A, bits 17 (MSB) through 0 (LSB). IN_A carries I samps in parallel input mode; I/Q
samps in muxed one-channel input mode
B10, A10, A9
IN_B[17:0]
P15, L14, P16, K14,
N15, N16, J14, M15,
M16, L15, L16, K15,
K16, J15, J16, H15,
I
Input Port B, bits 17 (MSB) through 0 (LSB) IN_B carries Q samples in parallel mode; I/Q
samples of second channel in 2-chan mode
H16, H14
IN_CLK
C12
I Input data clock (drives the PLL that generates CHIP_CLK)
Note: This pin is also the Scan clock, when GC1115 is in scan mode.
INT
A4
O INTERRUPT – Active low output
LOOP
P8
O Output pad for Tx PLL loop-back (MUST BE UNCONNECTED – NO LOAD!!)
OUT_A[17:0]
R5, P7, T4, R4, P6,
T3, R3, P2, P1, N2,
L3, N1, M2, K3, M1,
J3, L2, L1
O
Output Port A, bits 17 (MSB) through 0 (LSB)
OUT_A carries I samps in parallel output mode; I/Q samps in muxed 1-chan output mode
OUT_B[17:0]
T13, P11, R12, T12,
R11, P10, T11, R10,
P9, T10, R9, T9, T8,
R8, T7, R7, T6, R6
Output Port B, bits 17 (MSB) through 0 (LSB)
O OUT_B carries Q samples in parallel mode; I/Q samples of second channel in 2-channel
mode
OUT_CLK
K2
O Output data clock (do NOT use to drive other parts – for test purposes only!)
OUT_IQ_SEL T5
O Output I/Q select pin (low=I, high=Q) – only active in multiplexed I/Q output modes
RD
B6
I READ - Active low read input (option: ground RD to use WR as a WR/RD pin)
RESET
B13
I CHIP RESET – Active low input
SYNC_A
R14
I Input synchronization pin A (active low)
SYNC_B
T14
I Input synchronization pin B (active low)
SYNC_OUT R13
O Output sync pin (active low)
TCK
C8
I JTAG Clock
TDI
A8
I JTAG Data In
TDO
A7
O JTAG Data Out
TEST_MODE B7
I Test mode (not required for operation; pull to GND)
TMS
B9
I JTAG Mode Select
TRST
B8
I JTAG Reset (during GC1115 reset, TRST must be pulled low, then high)
VDD
C4, C13, D3, D5,
D12, D14, E4, E6,
E7, E8, E9, E10,
E11, E13, F5, F12,
G5, G12, H5, H12, I Digital core supply voltage, 1.2 V (40 pins)
J5, J12, K5, K12, L5,
L12, M4, M6–M11,
M13, N3, N5, N12,
N14, P4, P13
VDD1
B14
I Digital supply voltage for both PLLs (1 pin)
VDDA1
C16
I PLL 1 analog supply voltage (1 pin)
72
Submit Documentation Feedback