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GC1115_06 Datasheet, PDF (14/82 Pages) Texas Instruments – Crest Factor Reduction Processor
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GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
www.ti.com
The following constraints restrict the allowed combinations of the previously listed parameters:
1. Maximum input pin toggling rate: 130 MHz
2. Maximum output pin toggling rate in single-ended mode: 130 MHz
3. Maximum internal GC1115 clock rate: 305 MHz (IN_CLK x1, x2, x4)
4. Minimum PLL-driven internal GC1115 clock rate (at divide-by-1 PLL output): 100 MHz
5. Minimum IN_CLK rate: 25 MHz (using the 4x PLL multiplier with IN_CLK = 25 MHz generates the 100 MHz
minimum PLL output rate, at divide-by-1 PLL output)
Table 3 and Table 4 summarize the available one-channel and two-channel operating modes of the GC1115,
respectively.
INPUT
FORMAT
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
OUTPUT
FORMAT
Parallel
Parallel
Parallel
Parallel
Muxed
Muxed
Muxed
Muxed
Odd/Even
Odd/Even
Odd/Even
Odd/Even
Parallel
Parallel
Parallel
Parallel
Muxed
Muxed
Muxed
Muxed
Odd/Even
Odd/Even
Odd/Even
Odd/Even
Table 3. One-Channel Operating Modes
DECIM
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
INTERP
1
2c
1
2c
1
2c
1
2c
2r
4r
2r
4r
1
2c
1
2c
1
2c
1
2c
2r
4r
2r
4r
PLL MULT
4
4
2
2
4
4
2
2
4
4
2
2
2
2
1
1
2
2
1
1
2
2
1
1
IN_CLK
(MHz)
25 - 75
25 - 65
50 - 130
50 - 130
25 - 65
25 - 32.5
50 - 130
50 - 130
25 - 75
25 - 75
50 - 130
50 - 130
50 - 130
50 - 130
100 - 130
100 - 130
50 - 130
50 - 65
100 - 130
100 - 130
50 - 130
50 - 130
100 - 130
100 - 130
CORE CLK
(MHz)
100 - 305
100 - 260
100 - 260
100 - 260
100 - 260
100 - 305
100 - 260
100 - 260
100 - 305
100 - 305
100 - 260
100 - 260
100 - 260
100 - 260
100 - 130
100 - 130
100 - 260
100 - 130
100 - 130
100 - 130
100 - 260
100 - 260
100 - 130
100 - 130
OUT_CLK
(MHz)
25 - 80
50 - 130
25 - 65
50 - 130
50 - 130
100 - 130
50 - 130
50 - 130
50 - 160
100 - 250
100 - 250
100 - 250
25 - 65
50 - 130
25 - 32.5
50 - 65
50 - 130
100 - 130
25 - 32.5
50 - 65
25 - 65
50 - 130
25 - 32.5
50 - 65
fs/4 (MHz)
NA
NA
NA
NA
NA
NA
NA
NA
12.5 - 40
25 - 62.5
25 - 62.5
25 - 62.5
NA
NA
NA
NA
NA
NA
NA
NA
12.5 - 32.5
25 - 32.5
12.5 - 16.25
25 - 32.5
INPUT
FORMAT
Muxed
Muxed
Muxed
Muxed
Muxed
Muxed
OUTPUT
FORMAT
Muxed
Muxed
Muxed
Muxed
Real
Real
Table 4. Two-Channel Operating Modes
DECIM
1
1
2
2
1
2
INTERP
1
2c
1
2c
2r
2r
PLL MULT
4
4
2
2
4
2
IN_CLK
(MHz)
50 - 130
50 - 130
100 - 130
100 - 130
50 - 130
100 - 130
CORE CLK
(MHz)
100 - 260
100 - 260
100 - 130
100 - 130
100 - 260
100 - 130
OUT_CLK
(MHz)
50 - 130
100 - 260
50 - 65
100 - 130
50 - 130
50 - 130
fs/4 (MHz)
NA
NA
NA
NA
NA
NA
14
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