GC1115_06 Datasheet, PDF (67/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
www.ti.com
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
V_DD
V_DD1
V_DDA1,2
V_DDSHV
V_IN
T_Jmax
T_C
T_stg
Core supply voltage range
PLL digital supply voltage range
PLL analog supply voltage range
Input supply voltage range
Input voltage range
Maximum junction temperature
Operating case temperature
Storage temperature
UNIT
-0.3 V to 1.32 V
-0.3 V to 1.32 V
-0.3 V to 1.32 V
-0.3 V to 3.6 V
-0.3 V to V_DDSHV + 0.3 V
105°C
–40°C to +85°C
–55°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, V_SS
Core supply votlage, V_DD
PLL digital supply voltage, V_DD1
PLL analog supply voltage, V_DDA1,2
I/O supply voltage, V_DDSHV
Input voltage range, V_IN
Power consumption
Operating case temperature, T_C
Maximum junction temperature, T_Jmax
(1) Two-channel operation, IN_CLK = 80 MHz, decimate by 2, interpolate by 2.
MIN
1.14
1.08
1.14
3.0
3.0
-45
NOM
0
1.2
1.2
1.2
3.3
3.3
25
MAX
1.26
1.32
1.26
3.6
V_DDSHV
+ 0.3
3.3 ⁽¹⁾
85
105
UNIT
V
V
V
V
V
V
W
°C
°C
PACKAGE THERMAL RESISTANCE CHARACTERISTICS⁽¹⁾⁽²⁾
PACKAGE
IZDJ
AIRFLOW (m/sec)
0
1
2.5
θ_JA (°C/W)
18.3
16.2
15.3
θ_JB (°C/W)
10.0
10.0
10.0
θ_JC (°C/W)
5.9
5.9
5.9
(1) Simulations based on 1S2P board type as defined by JEDEC, tested at 85°C ambient temperature. Reference JEDEC Standard
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements.
(2) Adding thermal vias will significantly improve the thermal performance of the device. To use the thermal balls on the GC1115IZDJ
package:
• An array of 36 land pads must be added on the top layer of the PCB where the package will be mounted.
• The PCB land pads should be the same diameter as the vias in the package substrate for optimal board level reliability temperature
cycle performance.
• The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be
connected to the ground plane for heat dissipation.
• A solid internal plane is preferred for spreading the heat.
SWITCHING CHARACTERISTICS
JTAG:
tperiod
tjt_ckh
tjt_su
PARAMETER
JTAG clock period 14 ns
JTAG clock high time tjt_ckl JTAG clock low time
JTAG input (TDI or TMS) setup time before TCK goes high
MIN
MAX UNIT
14
ns
5
ns
1
ns
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