GC1115_06 Datasheet, PDF (37/82 Pages) Texas Instruments – Crest Factor Reduction Processor

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GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
CLK_CONTROL 0x2
Type: Read/Write Value at RESET: 0x1310
The CLK_CONTROL register provides separate bits to control the GC1115’s input, core, and output clocks. The
CLK_CONTROL register is unclocked, i.e. IN_CLK does not have to be toggling to change
CLK_CONTROL.
Figure 7 demonstrates how the various bits of the PLL_CONTROL and CLK_CONTROL registers interact to
determine various GC1115 clock frequencies.
BITS
[1:0]
2
3
[5:4]
[7:6]
[9:8]
[11:10]
[13:12]
[15:14]
DESCRIPTION
OUT_CLK source:
00: CLK_TX (after pad) 01: CLK_CORE (before buf)
10: CLK_CORE (after
buf)
11: CLK_TX (before pad)
IN_CLK edge selector 0 = rising, 1 = falling
PLL bypass
0 = use PLLs, 1 = bypass PLLs
Input clock rate:
00 – OFF
01 – inClk = PLL_CLK / 4
10 – inClk = PLL_CLK / 11 – inClk = PLL_CLK
2
Reserved
Core clock rate:
00 – OFF
01 – coreClk = PLL_CLK / 4
10 – coreClk = PLL_CLK 11 – coreClk = PLL_CLK
/2
Reserved
Output clock rate:
00 – OFF
01 – outClk = PLL_CLK / 4
10 – outClk = PLL_CLK / 11 – outClk = PLL_CLK
2
Reserved
CONTROL
0x3
Type: Read/Write Value at RESET: 0x0000
The CONTROL register provides separate bits to enable or to bypass the four peak detection and cancellation
(PDC) stages, the interpolate-by-4 block, and the soft limiter. If all bits are cleared, the GC1115 is in bypass
mode, during which no peaks are processed but the samples still flow through the GC1115’s internal delay
buffers.
BITS
0
1
2
3
4
5
[15:6]
PDC Stage 1
PDC Stage 2
PDC Stage 3
PDC Stage 4
Interpolator
Soft limiter
Reserved
DESCRIPTION
0 = bypassed, 1 = enabled
0 = bypassed, 1 = enabled
0 = bypassed, 1 = enabled
0 = bypassed, 1 = enabled
0 = bypassed, 1 = enabled
0 = bypassed, 1 = enabled
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