GC1115_06 Datasheet, PDF (24/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
www.ti.com
Writing Cancellation Coefficients to Shadow RAM
The GC1115 uses the CANCEL_ADDR register as a coefficient memory pointer to access cancellation
coefficient shadow RAM. This indirect addressing method requires only two registers (CANCEL_ADDR and
CANCEL_DATA) in the GC1115 memory map, while allowing GC1115 users access to 768 unique shadow
RAM addresses.
To access a particular shadow RAM location, the microprocessor or DSP that controls the GC1115 first writes
the desired address into the CANCEL_ADDR register. To write to the shadow RAM, the microprocessor or DSP
then writes the desired coefficient value to the CANCEL_DATA register. A write to (or read from) the
CANCEL_DATA register automatically post-increments the address in the CANCEL_ADDR register. The
following example demonstrates how the CANCEL_ADDR auto-increment feature is used to initialize the first
three cancellation coefficient shadow RAM locations mem(0), mem(1), and mem(2):
STEP
1
2
3
4
REGISTER
CANCEL_ADDR
CANCEL_DATA
CANCEL_DATA
CANCEL_DATA
VALUE
0
0x111
0x456
0x321
CANCEL_ADDR
AUTO-INCREMENT
0
0→1
1→2
2→3
COMMENTS
addr = 0
mem(0) = 0x111
mem(1) = 0x456
mem(2) = 0x321
Alternately, the microprocessor or DSP software can specify a shadow RAM address (0..767) with each
CANCEL_DATA access. This mode is useful when updating non-contiguous shadow RAM addresses. The
following example demonstrates how the CANCEL_ADDR direct-addressing mode is used to initialize the first
three cancellation coefficient shadow RAM locations mem(0), mem(2), and mem(1), in non-sequential order (just
to demonstrate the direct addressing capability):
STEP
1
2
3
4
5
6
REGISTER
CANCEL_ADDR
CANCEL_DATA
CANCEL_ADDR
CANCEL_DATA
CANCEL_ADDR
CANCEL_DATA
VALUE
0
0x111
2
0x321
1
0x456
CANCEL_ADDR
AUTO-INCREMENT
0
0→1
2
2→3
1
1→2
COMMENTS
addr = 0
mem(0) = 0x111
addr = 2
mem(2) = 0x321
addr = 1
mem(1) = 0x456
Shadow RAM and Canceler RAMs
The GC1115 contains eight unique canceler RAM memories that hold cancellation coefficients and their
derivatives. Each of the eight unique canceler RAMs can be accessed up to four times per IN_CLK clock period,
and each of the cancelers has its own canceler RAM pointer. This structure allows four cancelers to be
supported by one canceler RAM per IN_CLK clock period. This structure also makes it possible to store eight
different cancellation coefficient sets in the GC1115 (although this option is not recommended). With a total of
eight canceler RAMs, the GC1115 can have up to 32 cancelers running independently per channel (four
cancelers per canceler RAM per channel). Cancellation pulse resources are allocated in groups of four per
channel, i.e. one canceler RAM at a time, to the four PDC stages. The registers RESOURCE_CNT1 thru
RESOURCE_CNT4 specify how many canceler RAMs are allocated to each PDC stage. The total number of
resources cannot exceed 8.
The CANCEL_ADDR and CANCEL_DATA registers are used to write to an independent “shadow RAM”. Using
the CANCEL_ADDR and CANCEL_DATA registers, the GC1115’s controlling microprocessor or DSP writes
cancellation coefficients and derivative values to this shadow RAM, and not directly to the canceler RAMs
themselves. When a COEF_SYNC synchronization event occurs, the contents of the shadow RAM are copied
(one value per internal GC1115 clock cycle) to those canceler RAMs whose corresponding bit is set in the
RESOURCE_MASK register. Using the RESOURCE_CNT registers, cancelers may be separately taken off-line,
updated, and brought back on-line in seamless operation. This approach ensures that the GC1115 is never
without cancellation resources.
To summarize, cancellation coefficients and their derivatives are written to canceler RAMs as follows:
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