GC1115_06 Datasheet, PDF (73/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
www.ti.com
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (Alphabetical Listing) (continued)
NAME
VDDA2
VDDSHV
VPP
VSS
VSS1
VSSA1
VSSA2
WR
TERMINAL
NO.
C10
C5, D6–D11, E3,
E14, F4, F13, G4,
G13, H4, H13, J4,
J13, K4, K13, L4,
L13, M3, M14,
N6–N11, P5, P12
A11
A1, A2, A15, A16,
B1, B2, B15, B16,
C3, C14, D4, D13,
E5, E12, F6–F11,
G6–G11, H6–H11,
J6–J11, K6–K11,
L6–L11, M5, M12,
N4, N13, P3, P14,
R1, R2, R15, R16,
T1, T2, T15, T16,
C11
C15
A14
A5
I/O
DESCRIPTION
I PLL 2 analog supply voltage (1 pin)
I I/O supply voltage, 3.3 V (31 pins)
I E-fuse program supply voltage (not required for operation; pull to GND)
I Digital ground (64 pins)
I Digital ground for both PLLs (1 pin)
I PLL 1 analog ground (1 pin)
I PLL 2 analog ground (1 pin)
I WRITE - Active low write input (option: ground RD to use WR as a WR/RD pin)
Submit Documentation Feedback
73