GC1115_06 Datasheet, PDF (74/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
APPLICATION INFORMATION
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PC Board Layout Notes
1. Leave the LOOP pin unconnected.
2. Vpp is used only in manufacturing (for die ID). Attach Vpp via a pull-down resistor to GND.
3. SYNC_A and SYNC_B are input synchronization signals. SYNC_OUT is only needed to synchronize
multiple GC1115s, or if exact notification of a GC1115-internal event is needed (such as when a snapshot
RAM capture ends, or when the software timer count reaches zero). Wire SYNC_A, SYNC_B, and
SYNC_OUT_ to test points so they can be observed on a scope or logic analyzer.
4. During chip start-up, TRST must be pulled low and then high, or the GC1115 will not reset. A
general-purpose pin on the microprocessor or DSP that controls the GC1115 can do this operation. All other
JTAG signals are no-connects
5. Place power supply bypass caps on the back side of the board if possible.
Suggested Test Points:
• IN_CLK, OUT_CLK
• a few IN_A, IN_B, OUT_A, and OUT_B pins
• SYNC_A, SYNC_B, SYNC_OUT
• CS, RD, WR, plus a few A[ ] and D[ ] pins.
Power Connections
The PLL supplies should connect to dedicated pads with filtering as shown in Figure 16.
V_DD Supply
Series 50R
Ferrite Bead
0.1 µF
VDDA Dedicated Package
Pin and Bond Pad
0.01 µF
V_SS Supply
Series 50R
Ferrite Bead
VSSA Dedicated Package
Pin and Bond Pad
0.1 µF
VDD Dedicated Package
Pin and Bond Pad
0.01 µF
VSS Dedicated Package
Pin and Bond Pad
A. The 50R ferrite beads should be similar to: Murata P/N: BLM31P500SPT.
Figure 16. Power-Supply Filter
The PLL's analog supply wires
• should be 30 µm or wider and located in metal level 2, 3, or 4
• should be routed directly to the PLL's analog supply pads
• should avoid crossing or running parallel to any other supply or signal wires
Recommended GC1115 Board Bring-up Procedures
When customers bring up a GC1115-based printed circuit board for the first time, TI recommends the following
sequence of checks:
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