GC1115_06 Datasheet, PDF (54/82 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
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RESOURCE_CNT4 0x48 (72) Type: Read/Write Value at RESET: 0x0000
The RESOURCE_CNT4 register specifies how many canceler RAMs are associated with PDC Stage 4.
RESOURCE_CNT1 contains a value between 0 and 8. The sum of canceler RAMs in RESOURCE_CNT1,
RESOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 must be 8 or less. Resource allocations
become effective only after a RESOURCE_SYNC event occurs. The RESOURCE_SYNC register selects the
source of the RESOURCE_SYNC event.
BITS
[3:0]
[15:4]
DESCRIPTION
Number of canceler RAMs assigned to PDC Stage 4 (from 0 to 8)
Reserved
DETECT_TSQD4 0x49 (73) Type: Read/Write Value at RESET: 0x0000
The DETECT_TSQD4 register contains the detection threshold-squared value for PDC Stage 4. The detection
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 4 whose magnitude is above DETECT_TSQD4 will be decreased to the
magnitude-squared value specified in GAIN_TSQD4, assuming that PDC Stage 4 has an available canceler.
BITS
[15:0]
DESCRIPTION
Detection threshold-squared value for PDC Stage 4.
GAIN_TSQD4 0x4A (74) Type: Read/Write Value at RESET: 0x0000
The GAIN_TSQD4 register contains the gain threshold-squared value for PDC Stage 4. The gain
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 4 whose magnitude is above DETECT_TSQD4 will be decreased to the
magnitude-squared value specified in GAIN_TSQD4, assuming that PDC Stage 4 has an available canceler.
BITS
[15:0]
DESCRIPTION
Gain threshold-squared value for PDC Stage 4.
CANCEL_DELAY4 0x4B (75) Type: Read/Write
Value at RESET: 0x0000
The CANCEL_DELAY4 register contains the PDC Stage 4 cancellation pulse delay, in samples. For real
cancellation pulses, CANCEL_DELAY = (CANCEL_LENGTH – 1) / 2. If minimum-phase cancellation pulses are
used, CANCEL_DELAY < (CANCEL_LENGTH – 1) / 2. The contents of the CANCEL_DELAY4 register are
applied to the GC115 hardware delay block only after a CANCEL_SYNC event occurs.
BITS
[7:0]
[15:8]
DESCRIPTION
Cancel pulse delay for PDC Stage 4 (a value from 5 to 255)
Reserved
54
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