GC5330IZEV Datasheet, PDF (7/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
GC5330, GC5337
24 LVDS (1.8V) ^Baseband
Interface
24 LVDS (1.8V)
Power
Meter,
per
Channel
1–12 Channel DDUC Block
(config as TX or RX, showing TX)
FIR
1´,
2´
Farrow
1–1024´
CIC
1–3´
beAGC
per
Channel
TX
Complex
Gain per
Channel
Capture Buffer A
Capture Buffer B
Interval Based Power Meter
Running Avg Power Meter
Control and Sync CMOS (3.3 V)
NCO
X
TX
1–2 Streams
Mux
and
Sum
(TX)
or
Dist
(RX)
CFR
UC
1/2´
2´
Includes
interp ^{40% BW,}
before or ^{90 dB stop}
after CFR,
80% BW,
90 dB stop
RX 1/2/4 Streams
I/Q
Imbal
Correction
Eq
(16
Taps)
BDC
1/2/4/8/16´
IF
NCO
When I/Q correction
enabled, IF NCO is disabled
JTAG CMOS (3.3 V)
16
8
4
2
2
uP data uP addr uP ctrl INT TESTMOD, SPI en, SPIDIO SPIDO
RESET SPI clk
(SPARE)
4
JTAG
ET
DPD
and
TX
Eq
X
BUC
IF NCO
1/2/3/4´
80% BW,
90 dB stop;
90% BW,
80 dB stop
TX
IF
Mux
and
Sum
Switch
R2C
fe-
AGC
DC
Offset
Cancel
High-
Speed
Sync,
Clocks
40 LVDS (1.8V)
TX
Format
and
DAC
Interface
40 LVDS (1.8V)
1–4 TX Streams
Up to 8 DACs
(2 40-Pin Ports)
DVGA
Format/
GPIO
16 CMOS (3.3V)
ADC
inter-
face
(port
AB)
60 LVDS (1.8V)
Up to 8 ADCs
(2 30-Pin Ports)
ADC
inter-
face
(port C)
60 LVDS (1.8V)
1 ADC
(1 16-Pin Port)
DPD clk
2 LVDS
Sync A, B in 4 LVDS
Sync out
2 LVDS
LVDS
showing
the number
of pins;
each signal
is a diff pair
NOTE: UC1 and UC2 are for CFR interpolation; UC2 can only be used if UC1 is also used.
Figure 6. GC533x Block Diagram
B0445-01
GC533x Introduction
The GC533x is a flexible transmit and receive digital signal processor that includes receiver and transmitter
blocks, digital downconverter / upconverter (DDUC) blocks, crest factor reduction (CFR) and digital predistortion
(DPD) engines, flexible LVDS data converter and baseband interfaces, and capture buffers for DPD and adaptive
filtering algorithms.
Each of the four DDUC blocks can be configured as either a digital downconverter (DDC) or a digital upconverter
(DUC). Typically, a system can be implemented as both TX and RX, with both DDC and DUC functions. The
DDUC blocks provide programmable FIR filters with flexible numbers of taps, depending on signal bandwidth and
number of channels, as well as fractional resamplers, CIC filters, and complex mixers. The DDUC complex
mixers support static or hopping tuning functions.
beAGC after the DDC is part of the baseband interface. Static gain is applied in the BB block for both the DDC
output and DUC input.
The receiver block provides dc offset correction, front-end AGC, real-to-complex conversion, complex mixing,
decimating filters, a complex equalizer, and a blind RX IQ imbalance correction function.
The CFR block reduces the peak-to-average ratio (PAR) of complex, arbitrary TX signals. Reducing the PAR of
the TX signal allows wireless-infrastructure (WI) base stations and repeaters to use smaller and lower-cost
multi-carrier power amplifiers (MCPAs).
The DPD block can process one or two TX streams at 62 MHz {74 MHz} or four TX streams at 31 MHz {37 MHz}
each, with fifth-order nonlinear correction. The DPD engine uses a companion TI DSP TMS320C6748 to collect
the reference and feedback data, calculate the feedforward correction, and update the GC533x registers.
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