GC5330IZEV Datasheet, PDF (12/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
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Pin Functions (continued)
NAME
NUMBER
DVGA INTERFACE
DVGA[15:0]
AB11, AA10, Y10, AB12, AA11, Y11, AB13, AA12, Y12,
W12, AB14, AA13, Y13, AB15, AA14, Y14
MPU INTERFACE
UPD[15:0]
A11, C12, B12, A12, D13, C13, B13, A13, C14, B14, A14,
D15, C15, B15, A15, B16
UPA[7:0]
C9, B9, A9, C10, B10, A10, D11, C11
WEB
B11
EMIFENA
C8
OEB
D9
CEB
A8
JTAG INTERFACE
TRSTB
AA15
TMS
W15
TDO
W14
TDI
Y15
TCK
AB16
SPI INTERFACE
SPIDENB
A6
SPICLK
A7
SPIDIO
B7
SPIDO(SPARE) AA9
MISCELLANEOUS
TESTMOD
AB10
RESETB
Y9
INTERRPT
B8
DPDCLKP
C17
DPDCLKN
D17
SYNCOUTP
A19
SYNCOUTN
A18
SYNCAP
C16
SYNCAN
D16
SYNCBP
B18
SYNCBN
A17
TYPE
O
DESCRIPTION
I/O
I
I Write enable, active-low
I EMIFENA switches between address/data µP
access and SPI access. Its value may be changed
at any time, but both address/data access and SPI
access must be idle during the change. Logic 1 =
EMIF, logic 0 = SPI pin has internal pullup.
I Read and output enable, active-low
I Chip enable, active-low
I JTAG reset (active-low); pull down if JTAG is not
used.
I JTAG mode select
O JTAG data out
I JTAG data in
I JTAG clock
I Serial interface enable
I Serial interface clock
I/O Serial interface data
O Serial interface data out in four-wire SPI mode
I Test mode for GC533x, typically grounded
I Chip reset – required – active-low
O Output interrupt
I DPD CLK input – LVDS positive
I DPD CLK input – LVDS negative
O Sync output – LVDS positive
O Sync output – LVDS negative
I Sync input A – LVDS positive
I Sync input A – LVDS negative
I Sync input B – LVDS positive
I Sync input B – LVDS negative
1.8V
Ferrite Bead
R=0Ω
50 Ω
VDDA1 or VDDA2
GND
R=0Ω
50 Ω
C = 0.1 μF
C = 0.01 μF
VSSA1 or VSSA2
Ferrite Bead
NOTE: 0-Ω R0603 resistor is used to accommodate series resistor if needed.
Figure 8. GC533x PLL Filtering
S0510-01
12
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