GC5330IZEV Datasheet, PDF (15/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
I0-O
I0-E
Q0-O
Q0-E
I1-O
I1-E
Q1-O
Q1-E
In-O
In-E
Qn-O
Qn-E
00
‘n’ can be up to 47, ‘O’ is odd numbered bits (1, 3, 5, ...), ‘E’ is even numbered bits (0, 2, 4, ...)
I0-O
I0-E
Q0-O
Q0-E
BBIN Clk 0
BBIN Sync 0 Mode 1B
BBIN Data 0
I0-A
I0-B
I0-C
I0-D
Q0-A
Q0-B
Q0-C
Q0-D
In-A
In-B
In-C
In-D
Qn-A
Qn-B
Qn-C
Qn-D
00
I0-A
I0-A
I0-B
I0-C
I0-D
Q0-A
Q0-B
Q0-C
Q0-D
In-A
In-B
In-C
In-D
Qn-A
Qn-B
Qn-C
Qn-D
00
I0-A
‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs
BBIN Clk 0
BBIN Sync 0
BBIN Data 0
BBIN Clk 1
Mode 1N (1 Rate)
Mode 2N (2 Rates)
BBIN Sync 1
BBIN Data 1
I0-A
I0-B
I0-C
I0-D
I0-E
I0-F
I0-G
I0-H
Qn-A
Qn-B
Qn-C
Qn-D
Qn-E
Qn-F
Qn-G
Qn-H
00
I0-A
I0-A
I0-B
I0-C
I0-D
I0-E
I0-F
I0-G
I0-H
Qn-A
Qn-B
Qn-C
Qn-D
Qn-E
Qn-F
Qn-G
Qn-H
00
I0-A
I0-A
I0-B
I0-C
I0-D
I0-E
I0-F
I0-G
I0-H
Qn-A
Qn-B
Qn-C
Qn-D
Qn-E
Qn-F
Qn-G
Qn-H
00
I0-A
‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs
Figure 11. TX BB Formats
BBIN Clk 0
BBIN Sync 0
BBIN Data 0
BBIN Clk 1
BBIN Sync 1
BBIN Data 1
Mode 1S (1 Rate)
Mode 2S (2 Rates)
Mode 3S (3 Rates)
BBIN Clk 2
BBIN Sync 2
BBIN Data 2
T0504-01
The TX formatter block includes a per-channel TX gain adjust via a 16-bit complex digital word which can be set
to have gain between –∞ and 9 dB.
Digital Down- and Upconverters (DDUCs)
The GC533x has four identical and independent DDUC blocks that can be configured as either DDC or DUC.
Each DDUC can support up to 12 channels with scalable bandwidth.
The only difference between the DUC and DDC configurations is the interpolate (DUC) versus decimate (DDC)
functions and the data path direction as shown in Figure 12. Both DDC and DUC are described in this section.
Note that each DDUC block must be configured statically as a DUC or DDC and cannot switch modes
dynamically in TDD applications.
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