GC5330IZEV Datasheet, PDF (37/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
Table 17. General LVDS ADC Interface Table
ADC Type
Bits per Rail
ADS5400
1
ADS54RF63 (*)
1
ADS5463 (*)
1
ADS5474 (*)
1
RXA as baseband
TX input
2
ADS61xx, ADS41xx,
ADS62pxx
2
ADS55xx
2
ADS58B18
2
ADS58B28,
ADS62c1x
2
ADS64xx
6 or 7
ADS52xx
12 or 14
Clock
Centered
Yes
No
No
No
Yes
ADC Format
W7
W14
W14
W14
Baseband format – W14
ADC Input Timing Table
Table 18
Table 19
Table 19
Table 19
Table 21
Yes
B7
Yes
B7, W7
Yes
B7, W7
Yes
B7, W7
Yes
W7
Yes
W7
Table 20
Table 20Table 18
Table 20Table 18
Table 20Table 18
Table 18
Table 18
ADC Figure
Figure 20
Figure 20
Figure 20
Figure 20
Figure 20
Figure 20
Figure 20
Figure 20
Figure 20
Figure 21
Figure 21
Table 18. RX ADC-W7 Switching Characteristics
f_CLK(ADC)
t_su(ADC,A)
t_h(ADC,A)
t_su(ADC,B)
t_h(ADC,B)
PARAMETER
RX input clock frequency, ADCA7 Clk
Input data setup time on port A before ADCA7
Clk transition
Input data hold time on port A after ADCA7 Clk
transition
Input data setup time on port B before ADCB7
Clk transition
Input data hold time on port B after ADCB7 Clk
transition
TEST CONDITIONS
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
MIN NOM MAX UNIT
620 MHz
260
ps
170
ps
260
ps
140
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.
ADC Clock
ADC Data
t_su
t_h
t_h
t_su
T0512-01
Figure 20. RX ADC LVDS Timing Specifications (RXA and RXB)
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