GC5330IZEV Datasheet, PDF (30/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
Programmable trigger actions for alarm1:
www.ti.com
(0) No action
(1) Reduce gain of DPD output by programmable scale factor (programmed with
stream[n].gain_reduce), only if alarm caused by y(k) > high_threshold and alm_polarit = 0 or 2.
The gain reduction is applied at the CFR input. A control signal from the capture buffer block is
used to select the programmed gain value for the multiplier at the CFR input. When the host
resets this alarm by writing to the appropriate register, the control signal returns to 0 (state that is
not selecting the programmed gain value).
GENERAL SPECIFICATIONS
General Electrical Characteristics
This section describes the electrical characteristics for the CMOS interfaces (DVGA, MPU, JTAG, SPI,
TESTMOD, RESETB and INTERRPT) and LVDS interfaces (BBIN, BBOUT, TXA, TXB, RXA, RXB, RXC, SYNC,
DPDCLK) over recommended operating conditions (unless otherwise noted).
Table 9. General Electrical Characteristics, CMOS Interface
PARAMETER
V_IL
Voltage input low
V_IH
Voltage input high
V_OL
Voltage output low
V_OH
Voltage output high
|I_PU|
Pullup current
|I_PD|
Pulldown current
|I_IN|
Leakage current
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
I_OL = 2 mA⁽¹⁾
I_OH = –2 mA)⁽¹⁾
V_IN = 0 V⁽¹⁾
V_IN = V_DDSHV ⁽¹⁾
V_IN = 0 or V_DDSHV ^{(1) (2)}
MIN NOM
2
2.4
30 100
30 100
MAX
0.8
V_DDSHV
0.5
V_DDSHV
250
250
20
UNIT
V
V
V
V
µA
µA
µA
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) For inputs with no pullup or pulldown, inputs with pullup and V_IN = V_DDSHV, inputs with pulldown and V_IN = 0, and bidirectionals in input
mode in either state.
Table 10. General Electrical Characteristics, LVDS Interfaces
V_ICM
|V_P – V_N|
R_IN
V_COM
V_OD
PARAMETER
Input common mode voltage (V_P – V_N)/2
Input differential voltage
Input differential impedance
Output common-mode voltage
Ouput differential voltage
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽²⁾
See ⁽¹⁾
MIN
700
150
80
1125
250
NOM
92
1200
MAX
1500
700
120
1275
500
UNIT
mV
mV
Ω
mV
mV
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Characteristics are determined by design.
General Switching Characteristics
The baseband interface TX has a single DDR interface input mode. The customer logic and trace routing must
meet the listed t_su and t_h input timing.
30
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