GC5330IZEV Datasheet, PDF (41/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

www.ti.com
t
TCK
GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
TDI
t_SU
t_H
TDO
t_d
t_OH
Figure 24. JTAG Timing Specifications
T0289-02
The SPI programming interface is active only when EMIFENA is 0. There are both three-wire and four-wire SPI
interfaces; the SPIDO(SPARE) is the fourth wire for SPI data output.
Table 25. SPI Switching Characteristics
t_su(DENB)
t_su(DI)
t_h(DI)
t_d(DO)
t_d(DO1)
f_{clk SPI}
PARAMETER
Enable setup time before SPI CLK↑
Data setup time before SPI CLK↑
Input data hold time after CLK↑
Output data delay from f_TCK↓
Output data delay from f_TCK↓
SPI clock frequency
TEST CONDITIONS
Valid for SPIDENB, see⁽¹⁾
Valid for SPIDIO, see⁽¹⁾
Valid for SPIDIO, see⁽¹⁾
Valid for SPIDIO, see⁽²⁾
Valid for SPIDO(SPARE), see⁽²⁾
See ⁽¹⁾
MIN NOM MAX UNIT
5
ns
5
ns
0.6
ns
8 ns
8 ns
50 MHz
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) The SPI data output in three-wire mode comes from SPIDIO; in four-wire mode the output is from SPIDO(SPARE).
SPI Clock
SPIENB
SPIDIO-In
t_su(DENB)
t_h(DI)
t_su(DI)
SPIDO(SPARE)
t_d(DO1)
t_h(DO)
Figure 25. SPI Timing Specifications
T0516-01
© 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): GC5330 GC5337
Submit Documentation Feedback
41