GC5330IZEV Datasheet, PDF (32/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
www.ti.com
The lowest-rate outputs use DDR2 mode, where the output clock changes on one rising edge of the internal
clock and the output data changes on the subsequent rising edge. In DDR2 mode, the output bit rate (per LVDS
pair) is half of the internal clock. Middle-rate outputs use DDR1 mode, where the output clock changes on the
falling edge of the internal clock and the output data changes on the rising edge of the internal clock, which
results in an output bit rate equal to the internal clock rate. Both DDR1 and DDR2 result in the output clock edge
occurring in the middle of output data-stable time. The DDR1 and DDR2 modes are shown in Table 12 and
Figure 16.
The highest-rate outputs use DDR0 mode, where both the output clock and output data change with both the
rising and falling edges of the internal clock. The DDR0 output bit rate is twice the internal clock rate. DDR0
results in the clock and data changing at the same time, and typically requires extra trace length on the PC board
for the clockout signal to provide the required setup time for the receiving chip. The DDR0 mode is shown in
Table 13 and Figure 17.
Table 12. General Switching Characteristics, RX BB LVDS Output – DDR1, DDR2
PARAMETER
BASEBAND INTERFACE DDR LVDS
f_CLK(BB-DDR2)
f_CLK(BB-DDR1)
t_{skmin(BB)Serial0}
t_{skmax (BB)Serial0}
t_{skmin(BB)Serial1}
t_{skmax (BB)Serial1}
t_{skmin(BB)Serial2}
t_{skmin(BB)Serial2}
t_{skmax(BB)Nibble0}
t_{skmax(BB)Nibble0}
t_{skmin(BB)Nibble1}
t_{skmax(BB)Nibble1}
t_{skmin(BB)Byte}
Baseband output clock frequency
BBOUT3 Clk, BBOUT1:0 Data, BBOUT2 Sync
BBOUT3 Clk, BBOUT1:0 Data, BBOUT2 Sync
BBOUT7 Clk, BBOUT5:4 Data, BBOUT6 Sync
BBOUT7 Clk, BBOUT5:4 Data, BBOUT6 Sync
BBOUT11 Clk, BBOUT9:8 Data, BBOUT10 Sync
BBOUT11 Clk, BBOUT9:8 Data, BBOUT10 Sync
BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 Sync
BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 Sync
BBOUT7 Clk, BBOUT11:8 Data, BBOUT6 Sync
BBOUT7 Clk, BBOUT11:8 Data, BBOUT6 Sync
BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data, BBOUT6
Sync
t_{skmax(BB)Byte}
BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data, BBOUT6
Sync
TEST CONDITIONS
See ⁽¹⁾. Applies to BBOUT byte,
nibble, or serial
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
See ^{(2) (3)}
MIN NOM MAX UNIT
155
MHz
310
–20
ps
350
ps
15
ps
310
ps
60
ps
300
ps
170
ps
340
ps
55
ps
305
ps
250
ps
255
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Skew measured for RX BBOUT data and frame signals, relative to the BBclk signal at zero crossing. BBclk is measured at threshold
crossing. Lab measurement +signal → 50 Ω → Vcommon → 50 Ω → –signal. Vcommon has a 0.01-µF filter capacitor to GND.
Differential probe used for measurement.
(3) t_su calculation: 1/4 BBclk period – t_skmin; t_h calculation: 1/4 BBclk period – t_skmax
BBOUT Clk
BBOUT Sync
BBOUT Data
t_su
t_h
T0508-01
Figure 16. RX Baseband LVDS DDR1, DDR2 Output Timing Specifications
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