GC5330IZEV Datasheet, PDF (14/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
www.ti.com
Table 2. TX BB Formatter Modes
MODE
DESCRIPTION
1B
Byte mode, 1 interface rate
1N
Nibble mode, 1 interface rate
1S
Serial mode, 1 interface rate
2N
Nibble mode, 2 interface rates
2N’ ⁽¹⁾
2S
Nibble + byte mode, 2 interface
rates,
RX-ADC input pins used for
byte-mode port.
Serial mode, 2 interface rates
3S
Serial mode, 3 interface rates
Total Number of Interface Pins
10 or 11 = 8 or 9 data + 1 clk + 1
sync
6 = 4 data + 1 clk + 1 sync
4 = 2 data + 1 clk + 1 sync
12 = 4 data + 1 clk + 1 sync + 4
data + 1 clk + 1 sync
16 = 4 data + 1 clk + 1 sync + 8
data + 1 clk + 1 sync
Maximum Complex Interface Rate per Channel
N is the number of channels.
(Clk × 4/4)/N; maximum 192.31 MSPS total (for all
channels)
(Clk × 4/8)/N; maximum 125 (Nibble 0), 96.15 (Nibble
1) MSPS total
(Clk × 4/16)/N; maximum 48.07 MSPS total
(Clk × 4/8)/N × 2; maximum 221.15 MSPS total
Nibble port: (Clk × 4/8)/N; maximum 125 MSPS total
Byte port: (Clk × 2/4)/N; maximum 125, 250 MSPS
total
8 = 2 data + 1 clk + 1 sync + 2 data (Clk × 4/16)/N; maximum 96.15 MSPS total
+ 1 clk + 1 sync
12 = 2 data + 1 clk+1 sync + 2 data (Clk × 4/16)/N; maximum 144.23 MSPS total
+ 1 clk + 1 sync + 2 data + 1 clk + 1
sync
(1) 2N’ is the only configuration that allows a special mode to re-use RX input port A as baseband TX inputs
Table 3. TX BB Pin Assignments
LVDS PAIR BBI[11:0]
BBIN[0] pos. and neg.
BBIN[1] pos. and neg.
BBIN[2] pos. and neg.
BBIN[3] pos. and neg.
BBIN[4] pos. and neg.
BBIN[5] pos. and neg.
BBIN[6] pos. and neg.
BBIN[7] pos. and neg.
BBIN[8] pos. and neg.
BBIN[9] pos. and neg.
BBIN[10] pos. and neg.
BBIN[11] pos. and neg.
Number of BBdata streams
Number of DDR clocks to transfer 1 complex sample
BYTE MODE
BB0_DATA_0
BB0_DATA_1
BB0_DATA_2
Spare
BB0_DATA_3
BB0_DATA_4
BB0_SYNC
BB0_CLOCK
BB0_DATA_5
BB0_DATA_6
BB0_DATA_7
BB0_DATA_8
1
2
NIBBLE MODE
BB0_DATA_0
BB0_DATA_1
BB0_SYNC
BB0_CLOCK
BB0_DATA_2
BB0_DATA_3
BB1_SYNC
BB1_CLOCK
BB1_DATA_0
BB1_DATA_1
BB1_DATA_2
BB1_DATA_3
2
4
SERIAL MODE
BB0_DATA_0
BB0_DATA_1
BB0_SYNC
BB0_CLOCK
BB1_DATA_0
BB1_DATA_1
BB1_SYNC
BB1_CLOCK
BB2_DATA_0
BB2_DATA_1
BB2_SYNC
BB2_CLOCK
3
8
The actual data transfer rate in nibble mode is 2 times higher than the byte mode for the same total throughput. If
two ports are required (e.g., to support two different sample rates), and a lower speed on the interface is desired,
the GC533x can re-use the RX ADC input port A as a baseband TX input bus. RX ADC port A has 15 pairs of
LVDS input pins and supports one set of baseband input data in byte mode. When RX port A is used as a
baseband TX input, it cannot be also used as an RX input port.
The baseband interface supports a full-clock or gated-clock format. These formats are shown in Figure 11
The mapping for the RX port A pins when in BB TX input mode is:
• RXA14: clock
• RXA13: sync
• RXA12–5: BB0_DATA7–0
14
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