GC5330IZEV Datasheet, PDF (40/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
DPD Clock
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SYNCA, SYNCB
t_su
t_h
4 cycles, min.
Figure 22. SYNCA, SYNCB Timing to DPD Clock
T0514-01
Table 23. DPD Clock and Sync Out Switching Characteristics
t_d(SYNCOut)
t_HO(SYNCOut)
PARAMETER
Data valid after DPD clock
Data held valid after next DPD clock
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
MIN NOM MAX UNIT
0.95 ns
0.3
ns
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
Sync Out
DPD Clock
t_d
t_HO
T0515-01
Figure 23. Sync Out Timing to DPD Clock
The JTAG test connections are used with the CMOS signals for board interconnection tests. The TRSTB pin
must be toggled low, or low initially. If JTAG is not used, the TRSTB signal should be GROUNDed or tied to
GND through < 1 kΩ resistance. TRSTB should be 0 for normal operation.
Table 24. JTAG Switching Characteristics
f_TCK
t_TCKL
t_TCKH
t_su(TDI,TMS)
t_H(TDI,TMS)
t_d
t_OHD(TDO)
PARAMETER
JTAG clock frequency
JTAG clock low period
JTAG clock high period
Input data setup time before f_TCK↑
Input data hold time after f_TCK↑
Output data delay from f_TCK↓
Previous data valid from f_TCK↓
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
MIN MAX UNIT
50 MHz
10
ns
10
ns
7 ns
1.5
10 ns
2 ns
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
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