GC5330IZEV Datasheet, PDF (31/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
Table 11. General Switching Characteristics, TX BB LVDS Input
PARAMETER
BASEBAND INTERFACE DDR LVDS
f_{CLK(BB-Serial)}
f_{CLK(BB-Nibble)} Baseband input clock frequency
f_CLK(BB-Byte)
f_CLK(RXA)
t_su(BBS0)
t_hi(BBS0)
t_su(BBS1)
t_hi(BBS1)
t_su(BBS2)
t_hi(BBS2)
t_su(BBN0)
t_h(BBN0)
t_su(BBN1)
t_h(BBN1)
t_su(BB)
t_h(BB)
Baseband input clock frequency, using RXA
BBIN3 Clk, BBIN1:0 Data, BBIN2 Sync
BBIN3 Clk, BBIN1:0 Data, BBIN2 Sync
BBIN7 Clk, BBIN5:4 Data, BBIN6 Sync
BBIN7 Clk, BBIN5:4 Data, BBIN6 Sync
BBIN11 Clk, BBIN9:8 Data, BBIN10 Sync
BBIN11 Clk, BBIN9:8 Data, BBIN10 Sync
BBIN3 Clk, BBIN5,4,1,0 Data, BBIN2 Sync
BBIN3 Clk, BBIN5,4,1,0 Data, BBIN2 Sync
BBIN7 Clk, BBIN11:8 Data, BBIN6 Sync
BBIN7 Clk, BBIN11:8 Data, BBIN6 Sync
BBIN7 Clk, BBIN11:8,5:4,2:0 Data, BBIN6 Sync
BBIN7 Clk, BBIN11:8,5:4,2:0 Data, BBIN6 Sync
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
MIN NOM MAX UNIT
384
500(Nibble0)
384(Nibble1)
384
250
250
200
210
250
240
190
250
220
250
220
280
250
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Setup and hold times are measured from differential data crossing zero to differential clock crossing zero.
BBIN Clk
BBIN Data, BBIN Sync
t_su
t_h
t_h
t_su
T0507-01
Figure 15. TX Baseband LVDS Input Timing Specifications
The BB LVDS RX outputs have three different output timing modes, DDR0, DDR1 and DDR2. DDR1 and DDR2
modes output data, and the BBclk output is centered over the data. In DDR0 mode, the data and clock are
edge-aligned. Different BBOUT pins are used for clock, frame, and data pins depending on the byte, nibble, and
serial modes. The DDR1 and DDR2 modes are shown in Table 12 and Figure 16. The DDR0 mode is shown in
Table 13 and Figure 17. Table 12 and Figure 16. DDR1 mode is used upto a BBclk frequency of 310 MHz.
DDR2 mode is used upto a BBclk frequency of 155 MHz. When the data rate is higher than 500 MHz, BBclk
above 250 MHz, the operating mode is DDR0. In this mode, the clock is aligned with the output data transition. In
DDR0 mode, the customer must delay the clock to meet the t_su and t_hi target for the baseband input. The t_skw
time is measured as the relative skew for the data and frame to the clock output. This is shown in Figure 13 and
Table 17.
In receive (uplink) mode, the GC5330 outputs data using the LVDS pins BBOUT. The BBOUT port may be
operated in three modes, DDR0, DDR1, and DDR2.
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