GC5330IZEV Datasheet, PDF (13/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
The two GC533x PLLs require a filtered power supply. The supply can be generated by filtering the digital supply
(VDDS1, VSSA1, VDDS2, and VSSA2). A representative filter is shown in Figure 8. The two PLLs should have
separate filters that are located as close as is reasonable to their respective pins (especially the bypass
capacitors). The ferrite beads should be series 50R (similar to Murata P/N: BLM31P500SPT, Description: IND FB
BLM31P500SPT 50R 1206).
Sub-Chip Descriptions
Figure 9 shows the TX functional block diagram, and Figure 10 shows the RX functional block diagram. Note that
each figure shows up to four DUC or DDC blocks in the TX or RX paths, and there are a total of four DDUC
blocks that may be configured as either DUC or DDC each.
Envelope
Tracking
Block
TX BB
1–12 Channel DUC Block
NCO
FIR
1x, 2x
Farrow
1–1024x
CIC
1–3x
X
1–2 Streams
TX Block
Mux
and
Sum
UC
1/2x
CFR
UC
1/2/4x
DPD
80% BW,
90 dBstop
40% BW, Includes
90 dBstop 16-tap Eq
BUC
IF
NCO
IF
Sum
1/2/3/4x
80% BW,
90 dBstop;
90% BW,
80% dB stop
Figure 9. TX Functional Block Diagram
1 to 4 Tx
Streams
B0446-01
RX BB
1–12 Channel DDC Block
NCO
FIR
1´, 2x
Farrow
1–1024´
CIC
1–3´
X
1/2/4 Streams
I/Q
Imbalance
Correction
RX
Equalizer
16 Taps
BDC
Mux
When I/Q
correction
enabled,
IF NCO
is disabled
1/2/4/8/16´
Figure 10. RX Functional Block Diagram
RX Block
X
1 to 9
ADC
Inputs
IF _{IF NCO}
Mux
R2C;
Format;
feAGC;
DC Offset
X
Correction
IF NCO
DVGA Outputs
B0447-01
TX Baseband Input Formatter
The TX baseband (BB) input-formatter block accepts TX baseband inputs from the FPGA or baseband processor
and formats them for the DUC blocks. There are 12 unidirectional LVDS pairs for the TX input formatter, and
their function depends on the operational mode. There are three operational modes for the TX BB input
formatter: byte mode (B, 8 or 9 bits), nibble mode (N, 4 bits), and serial mode (S, 2 bits) to allow multiple BB
input rates. The GC533x can accept up to three different BB input data rates. Table 2 and Table 3 summarize
each mode and the pin assignments. In Table 3, BBIN[X] is the BBIN differential pair (assumed positive and
negative connections), and BB0, BB1, and BB2 represent three different TX baseband ports at arbitrary rates.
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